On 09/07/2016 03:28 PM, Chin Liang See wrote:
> On Tue, 2016-09-06 at 14:09 +0200, Marek Vasut wrote:
>> On 09/06/2016 08:19 AM, Chin Liang See wrote:
>>> On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:
>>>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>>>> Segregate the misc.c to support both GEN5 SoC and Stratix 10
>>>>> SoC.
>>>>>
>>>>> Signed-off-by: Chin Liang See <cl...@altera.com>
>>>>> Cc: Marek Vasut <ma...@denx.de>
>>>>> Cc: Dinh Nguyen <dingu...@opensource.altera.com>
>>>>> Cc: Ley Foon Tan <lf...@altera.com>
>>>>> ---
>>>>> arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
>>>>> 1 file changed, 12 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach
>>>>> -socfpga/misc.c
>>>>> index 5cbd8a4..295121f 100644
>>>>> --- a/arch/arm/mach-socfpga/misc.c
>>>>> +++ b/arch/arm/mach-socfpga/misc.c
>>>>> @@ -24,6 +24,8 @@
>>>>>
>>>>> DECLARE_GLOBAL_DATA_PTR;
>>>>>
>>>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>>> +
>>>>> static struct pl310_regs *const pl310 =
>>>>> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>>>>> static struct socfpga_system_manager *sysmgr_regs =
>>>>> @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
>>>>> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>>>>> static struct scu_registers *scu_regs =
>>>>> (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>>>>> +#endif
>>>>>
>>>>> int dram_init(void)
>>>>> {
>>>>> @@ -41,6 +44,7 @@ int dram_init(void)
>>>>> return 0;
>>>>> }
>>>>>
>>>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>>> void enable_caches(void)
>>>>> {
>>>>> #ifndef CONFIG_SYS_ICACHE_OFF
>>>>> @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool
>>>>> print_id)
>>>>> socfpga_fpga_model[i].name, version);
>>>>> return i;
>>>>> }
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>>
>>>>> /*
>>>>> * Print CPU information
>>>>> @@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool
>>>>> print_id)
>>>>> #if defined(CONFIG_DISPLAY_CPUINFO)
>>>>> int print_cpuinfo(void)
>>>>> {
>>>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>>> const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
>>>>> puts("CPU: Altera SoCFPGA Platform\n");
>>>>> socfpga_fpga_id(1);
>>>>> printf("BOOT: %s\n", bsel_str[bsel].name);
>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>>>> + puts("CPU: Altera SoCFPGA Platform\n");
>>>>> + puts("FPGA: Altera Stratix 10\n");
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>
>>>> Can't you decode the boot mode and FPGA type instead ?
>>>
>>> That is a good question. This is now not available in SOC Virtual
>>> Platform. But will definitely enhance this in later stage with
>>> hardware
>>> available.
>>
>> What do you mean not available ? Does the VT not emulate the SoC
>> precisely ?
>>
>
> The VT doesn't emulate the Secure Device Manager (SDM) part as its
> focusing on ARM64 for this phase.
And the SDM is now the place from which you fish out the information
about the FPGA and bootmode ?
--
Best regards,
Marek Vasut
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