[U-Boot] [PATCH v3 10/12] arm: dts: socfpga: Add dts for Stratix 10 socdk

[Chin Liang See]

Add device tree for Stratix 10 SoC development kit

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
Acked-by: Marek Vasut <ma...@denx.de>
---
Changes for v3
- Changed to correct file mode
- Removed trampoline code
- Fixed the DDR size to 2GB and SDMMC interrupt to 96
---
 arch/arm/dts/Makefile                    |  3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 71 ++++++++++++++++++++++++++++++++
 2 files changed, 73 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8458f6b..1809660 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -131,7 +131,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=                               
\
        socfpga_cyclone5_sockit.dtb                     \
        socfpga_cyclone5_socrates.dtb                   \
        socfpga_cyclone5_sr1500.dtb                     \
-       socfpga_cyclone5_vining_fpga.dtb
+       socfpga_cyclone5_vining_fpga.dtb                \
+       socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
        dra72-evm-revc.dtb
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 0000000..bb65f2b
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,71 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+
+/ {
+       model = "Altera SOCFPGA Stratix 10 SoC Development Kit";
+       compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x80000000>; /* 2GB */
+       };
+
+       regulator_3_3v: 3-3-v-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               ranges;
+               u-boot,dm-pre-reloc;
+
+               mmc0: dwmmc0@0xff808000 {
+                       compatible = "altr,socfpga-dw-mshc";
+                       reg = <0xff808000 0x1000>;
+                       interrupts = <0 96 4>;
+                       num-slots = <1>;
+                       broken-cd;
+                       bus-width = <4>;
+                       fifo-depth = <0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cap-mmc-highspeed;
+                       cap-sd-highspeed;
+                       drvsel = <3>;
+                       smplsel = <0>;
+                       status = "okay";
+                       u-boot,dm-pre-reloc;
+                       vmmc-supply = <&regulator_3_3v>;
+                       vqmmc-supply = <&regulator_3_3v>;
+               };
+
+               uart0: serial0@ffc02000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc02000 0x1000>;
+                       interrupts = <0 108 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "okay";
+               };
+       };
+};
-- 
2.2.2

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