On Wednesday 19 October 2016 08:58 PM, Marek Vasut wrote: > On 10/19/2016 05:19 PM, Jagan Teki wrote: >> On Wed, Oct 19, 2016 at 8:18 PM, Marek Vasut <ma...@denx.de> wrote: >>> On 10/19/2016 04:41 PM, Jagan Teki wrote: >>>> On Wed, Oct 19, 2016 at 10:10 AM, Vignesh R <vigne...@ti.com> wrote: >>>>> Hi, ... >>>>>> You can probably pull this block from the else branch. >>>>> >>>>> Yeah, I guess writesb() can handle zero byte write request I believe. >>>>> >>>>> With above change, can I have your Acked-by/Reviewed-by? >>>> >>>> Also try to get the 'sf update' data before and after and append it on >>>> commit message. >>> >>> Why? Seems useless to me. >> >> Since it's a performance improvement patch better to have that >> numbers, no harm getting that data. > > Urghhhh, sf update is mixing multiple access patterns, it is by no means > a good performance metric for evaluating performance of the > write path. > > What you would need to do here is perform long unaligned writes > repeatedly (to eliminate outliers) and measure the improvement. > And you'd have to make sure the erase cycle is not counted in. > > I suspect the performance improvement would be negligible, but > I'd be happy to be proven wrong. If it'd be negligible, then > we should probably not complicate the code more and just drop > this patch. >
Today, I was performing unaligned writes of various sizes to get performance numbers and discovered that unaligned writes (i.e txbuf address is not word aligned or write_byte % 4 != 0) are sometimes failing on TI platforms with Cadence QSPI (with or w/o this patch) :( Reverting the patch "mtd: cqspi: Simplify indirect write code" seems to be helping. I don't see anything obviously wrong here. Let me debug whats causing the difference and get back. -- Regards Vignesh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot