On 19 October 2016 at 15:18, Stephen Warren <swar...@wwwdotorg.org> wrote: > From: Stephen Warren <swar...@nvidia.com> > > SoC-specific logic may be required for all forms of cache-wide > operations; invalidate and flush of both dcache and icache (note that > only 3 of the 4 possible combinations make sense, since the icache never > contains dirty lines). This patch adds an optional hook for all > implemented cache-wide operations, and renames the one existing hook to > better represent exactly which operation it is implementing. A dummy > no-op implementation of each hook is provided. > > Signed-off-by: Stephen Warren <swar...@nvidia.com> > --- > v2: > * Implement all dummy/weak functions in assembly, since some cache > operations cannot access DRAM/stack. > * Rename hook functions with __asm prefix etc. > --- > arch/arm/cpu/armv8/cache.S | 18 +++++++++++++++--- > arch/arm/cpu/armv8/cache_v8.c | 8 +++++--- > arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ++-- > arch/arm/include/asm/system.h | 4 +++- > arch/arm/mach-tegra/tegra186/cache.S | 4 ++-- > 5 files changed, 27 insertions(+), 11 deletions(-)
Reviewed-by: Simon Glass <s...@chromium.org> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
