> -----Original Message----- > From: Prabhakar Kushwaha > Sent: Thursday, October 20, 2016 9:03 AM > To: u-boot@lists.denx.de > Cc: Priyanka Jain <priyanka.j...@nxp.com> > Subject: RE: [U-Boot] [PATCH 4/5] armv8: fsl-layerscape: Add NXP LS2088A > SoC support > > > > -----Original Message----- > > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of > > Priyanka Jain > > Sent: Wednesday, October 19, 2016 3:07 PM > > To: u-boot@lists.denx.de > > Cc: Priyanka Jain <priyanka.j...@nxp.com> > > Subject: [U-Boot] [PATCH 4/5] armv8: fsl-layerscape: Add NXP LS2088A > > SoC support > > > > The QorIQ LS2088A SoC is built on layerscape architecture. > > > > It is similar to LS2080A SoC with some differences like 1)Timer > > controller offset is different 2)It has A72 cores 3)It supports TZASC > > module > > > > Signed-off-by: Priyanka Jain <priyanka.j...@nxp.com> > > --- > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 > > +++++++++++++++++++++ > > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++- > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + > > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++ > > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++ > > board/freescale/ls2080a/MAINTAINERS | 2 +- > > board/freescale/ls2080aqds/MAINTAINERS | 2 +- > > board/freescale/ls2080aqds/README | 12 ++-- > > board/freescale/ls2080ardb/MAINTAINERS | 2 +- > > board/freescale/ls2080ardb/README | 8 ++-- > > 10 files changed, 84 insertions(+), 15 deletions(-) > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > index f7b949a..c7496c0 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > @@ -4,6 +4,7 @@ SoC overview > > 2. LS2080A > > 3. LS1012A > > 4. LS1046A > > + 5. LS2088A > > > > LS1043A > > --------- > > @@ -169,3 +170,60 @@ The LS1046A SoC includes the following function > > and > > features: > > - Two DUARTs > > - Integrated flash controller (IFC) supporting NAND and NOR flash > > - QorIQ platform's trust architecture 2.1 > > + > > +LS2088A > > +-------- > > +The LS2088A integrated multicore processor combines eight ARM > > +Cortex-A72 processor cores with high-performance data path > > +acceleration logic and > > network > > +and peripheral bus interfaces required for networking, > > +telecom/datacom, wireless infrastructure, and mil/aerospace > applications. > > + > > +The LS2088A SoC includes the following function and features: > > + > > + - Eight 64-bit ARM Cortex-A72 CPUs > > + - 1 MB platform cache with ECC > > + - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving > > support > > + - One secondary 32-bit DDR4 SDRAM memory controller, intended for > use by > > + the AIOP > > + - Data path acceleration architecture (DPAA2) incorporating acceleration > for > > + the following functions: > > + - Packet parsing, classification, and distribution (WRIOP) > > + - Queue and Hardware buffer management for scheduling, packet > > sequencing, and > > + congestion management, buffer allocation and de-allocation (QBMan) > > + - Cryptography acceleration (SEC) at up to 10 Gbps > > + - RegEx pattern matching acceleration (PME) at up to 10 Gbps > > + - Decompression/compression acceleration (DCE) at up to 20 Gbps > > + - Accelerated I/O processing (AIOP) at up to 20 Gbps > > + - QDMA engine > > + - 16 SerDes lanes at up to 10.3125 GHz > > + - Ethernet interfaces > > + - Up to eight 10 Gbps Ethernet MACs > > + - Up to eight 1 / 2.5 Gbps Ethernet MACs > > + - High-speed peripheral interfaces > > + - Four PCIe 3.0 controllers, one supporting SR-IOV > > + - Additional peripheral interfaces > > + - Two serial ATA (SATA 3.0) controllers > > + - Two high-speed USB 3.0 controllers with integrated PHY > > + - Enhanced secure digital host controller (eSDXC/eMMC) > > + - Serial peripheral interface (SPI) controller > > + - Quad Serial Peripheral Interface (QSPI) Controller > > + - Four I2C controllers > > + - Two DUARTs > > + - Integrated flash controller (IFC 2.0) supporting NAND and NOR > > + flash > > + - Support for hardware virtualization and partitioning enforcement > > + - QorIQ platform's trust architecture 3.0 > > + - Service processor (SP) provides pre-boot initialization and > > + secure-boot capabilities > > + > > +LS2088A SoC has 3 more similar SoC personalities 1)LS2048A, few > > +difference w.r.t. LS2088A: > > + a) Four 64-bit ARM v8 Cortex-A72 CPUs > > + > > +2)LS2084A, few difference w.r.t. LS2088A: > > + a) No AIOP > > + b) No 32-bit DDR3 SDRAM memory > > + c) 5 * 1/10G + 5 *1G WRIOP > > + d) No L2 switch > > + > > +3)LS2044A, few difference w.r.t. LS2084A: > > + a) Four 64-bit ARM v8 Cortex-A72 CPUs > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > index d68eeba..d43361f 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > > @@ -31,8 +31,10 @@ bool soc_has_dp_ddr(void) > > struct ccsr_gur __iomem *gur = (void > *)(CONFIG_SYS_FSL_GUTS_ADDR); > > u32 svr = gur_in32(&gur->svr); > > > > - /* LS2085A has DP_DDR */ > > - if (SVR_SOC_VER(svr) == SVR_LS2085A) > > + /* LS2085A, LS2088A, LS2048A has DP_DDR */ > > + if ((SVR_SOC_VER(svr) == SVR_LS2085A) || > > + (SVR_SOC_VER(svr) == SVR_LS2088A) || > > + (SVR_SOC_VER(svr) == SVR_LS2048A)) > > return true; > > > > return false; > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > > index 4201e0f..6c3ba49 100644 > > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > > @@ -25,6 +25,7 @@ > > #ifndef L1_CACHE_BYTES > > #define L1_CACHE_SHIFT 6 > > #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) > > +#define CONFIG_FSL_TZASC_400 > > Looks like this is getting enabled even for LS2080, LS2085A. > Will it not create any problem? > > --prabhakar As both LS2088A, LS2080A share same config file, CONFIG_FSL_TZASC_400 is enabled by default. Another patch " [PATCH 3/5] armv8: fsl-layerscape : Check SVR for initializing TZASC" checks SVR before doing TZASC operations. So, this ensures that things work fine on LS2080, LS2085 as well
--Priyanka _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot