On 10/30/2016 06:19 PM, Eric Nelson wrote: > The DDR calibration routines have scattered support for bus > widths other than 64-bits: > > -- The mmdc_do_write_level_calibration() routine assumes the > presence of PHY1, and > -- The mmdc_do_dqs_calibration() routine tries to determine > whether one or two DDR PHYs are active by reading MDCTL. > > Since a caller of these routines must have a valid struct mx6_ddr_sysinfo > for use in calling mx6_dram_cfg(), and the bus width is available in the > "dsize" field, use this structure to inform the calibration routines which > PHYs are active. > > This allows the use of the DDR calibration routines on CPU variants > like i.MX6SL that only have a single MMDC port. > > Signed-off-by: Eric Nelson <e...@nelint.com>
Reviewed-by: Marek Vasut <ma...@denx.de> -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
