PSCI implementation needs the SMC instruction to be enabled.
Signed-off-by: Hongbo Zhang <hongbo.zh...@nxp.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
---
arch/arm/include/asm/macro.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 2553e3e..e1916f7 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -182,11 +182,17 @@ lr .req x30
/*
* The next lower exception level is AArch64, 64bit EL2 | HCE |
- * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * and the SMD depends on requirements.
*/
+#ifdef CONFIG_ARMV8_PSCI
+ ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+ SCR_EL3_RES1 | SCR_EL3_NS_EN)
+#else
ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
+#endif
msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */
--
2.1.4
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