On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.c...@intel.com>
>
> The system manager on Arria10 is not used for pin muxing duties, so wrap
> these functions for GEN5 devices only.
>
> Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> Cc: Marek Vasut <ma...@denx.de>
> Cc: Dinh Nguyen <dingu...@kernel.org>
> Cc: Chin Liang See <chin.liang....@intel.com>
> Cc: Tien Fong <skywind...@gmail.com>
> ---
> arch/arm/mach-socfpga/system_manager.c | 2 ++
Use Makefile condition to exclude this from being compiled altogether.
btw I wonder how you can add the Arria10 SoCDK support first and only
then add infrastructure like this. Please reorder the patches so that
the groundwork is in place before you add the actual device support.
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/system_manager.c
> b/arch/arm/mach-socfpga/system_manager.c
> index 75a65f3..9e1c3fd 100644
> --- a/arch/arm/mach-socfpga/system_manager.c
> +++ b/arch/arm/mach-socfpga/system_manager.c
> @@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
> * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
> * CONFIG_SYSMGR_ISWGRP_HANDOFF.
> */
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> static void populate_sysmgr_fpgaintf_module(void)
> {
> uint32_t handoff_val = 0;
> @@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
> clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
> SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
> }
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
--
Best regards,
Marek Vasut
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