On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.c...@intel.com>
>
> On the Arria10, the EMAC phy mode configuration for each EMACs is located
> in separate registers versus being in 1 register for the GEN5 devices. The
> Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
>
> Update the dwmac_deassert_reset function to support both GEN5 and Arria10
> devices.
>
> Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> Cc: Marek Vasut <ma...@denx.de>
> Cc: Dinh Nguyen <dingu...@kernel.org>
> Cc: Chin Liang See <chin.liang....@intel.com>
> Cc: Tien Fong <skywind...@gmail.com>
> ---
> arch/arm/mach-socfpga/include/mach/system_manager.h | 4 +---
> arch/arm/mach-socfpga/misc.c | 14 ++++++++++++++
> 2 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h
> b/arch/arm/mach-socfpga/include/mach/system_manager.h
> index 9ca889a..831ba4a 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> @@ -133,9 +133,7 @@ struct socfpga_system_manager {
> u32 usb0_l3master;
> u32 usb1_l3master;
> u32 emac_global;
> - u32 emac0;
> - u32 emac1;
> - u32 emac2;
> + u32 emac[3];
> u32 _pad_0x50_0x5f[4];
> u32 fpgaintf_en_global;
> u32 fpgaintf_en_0;
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index c97caea..510aa1d 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -21,7 +21,11 @@
> #include <asm/arch/scu.h>
> #include <asm/pl310.h>
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> #include <dt-bindings/reset/altr,rst-mgr.h>
> +#else
> +#include <dt-bindings/reset/altr,rst-mgr-a10.h>
> +#endif
IMO it'd be better to have a "proxy" reset manager header, which would
include either rst-mgr-gen5.h or rst-mgr-a10.h depending on the type of
SoC used. That way you'd be able to avoid this ifdeffering in each file
including rst-mgr-*h
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int
> of_reset_id,
> } else if (of_reset_id == EMAC1_RESET) {
> physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
> reset = SOCFPGA_RESET(EMAC1);
> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
More like ifdef arria10 here, no ?
> + } else if (of_reset_id == EMAC2_RESET) {
> + reset = SOCFPGA_RESET(EMAC2);
> +#endif
> } else {
> printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
> return;
> }
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> /* configure to PHY interface select choosed */
> clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
> SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
> phymode << physhift);
> +#else
> + clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
> + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
> + phymode);
> +#endif
>
> /* Release the EMAC controller from reset */
> socfpga_per_reset(reset, 0);
>
--
Best regards,
Marek Vasut
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