On 01/24/2017 02:34 AM, Prabhakar Kushwaha wrote:
> IFC IP clock is always a constant divisor of platform clock
> pre-defined per SoC. Clock control register (CCR) used in
> current implementation governs IFC IP output clock.
>
> So update IFC IP clock to be defined as per predefined clock
> divisor of platform clock.
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
> ---
> Changes for v2: Split the patch in 2 patch set
> Changes for v3: Rebased on top of u-boot commit
> Changes for v4: fix compilation error
> Changes for v5: Adding FSL_IFC as dependency
>
> README | 3 +++
> arch/powerpc/cpu/mpc85xx/Kconfig | 16 ++++++++++++++++
> arch/powerpc/cpu/mpc85xx/speed.c | 10 ++--------
> 3 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/README b/README
> index a95348a..9fda381 100644
> --- a/README
> +++ b/README
> @@ -504,6 +504,9 @@ The following options need to be configured:
> CONFIG_SYS_FSL_IFC_LE
> Defines the IFC controller register space as Little Endian
>
> + CONFIG_SYS_FSL_IFC_CLK_DIV
> + Defines divider of platform clock(clock input to IFC
> controller).
> +
> CONFIG_SYS_FSL_PBL_PBI
> It enables addition of RCW (Power on reset configuration) in
> built image.
> Please refer doc/README.pblimage for more details
> diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig
> b/arch/powerpc/cpu/mpc85xx/Kconfig
> index c67b6b0..8c6503d 100644
> --- a/arch/powerpc/cpu/mpc85xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc85xx/Kconfig
> @@ -1265,6 +1265,22 @@ config SYS_PPC_E500_DEBUG_TLB
> symbol should be set to the TLB1 entry to be used for this
> purpose. If unsure, do not change.
>
> +config SYS_FSL_IFC_CLK_DIV
> + int "Divider of platform clock"
> + depends on FSL_IFC
> + default 2 if ARCH_B4420 || \
> + ARCH_B4860 || \
> + ARCH_T1024 || \
> + ARCH_T1023 || \
> + ARCH_T1040 || \
> + ARCH_T1042 || \
> + ARCH_T4160 || \
> + ARCH_T4240
> + default 1
> + help
> + Defines divider of platform clock(clock input to
> + IFC controller).
> +
> source "board/freescale/b4860qds/Kconfig"
> source "board/freescale/bsc9131rdb/Kconfig"
> source "board/freescale/bsc9132qds/Kconfig"
> diff --git a/arch/powerpc/cpu/mpc85xx/speed.c
> b/arch/powerpc/cpu/mpc85xx/speed.c
> index fcf5d92..adba092 100644
> --- a/arch/powerpc/cpu/mpc85xx/speed.c
> +++ b/arch/powerpc/cpu/mpc85xx/speed.c
> @@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
> void get_sys_info(sys_info_t *sys_info)
> {
> volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> -#ifdef CONFIG_FSL_IFC
> - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
> - u32 ccr;
> -#endif
> #ifdef CONFIG_FSL_CORENET
> volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
> unsigned int cpu;
> @@ -640,10 +636,8 @@ void get_sys_info(sys_info_t *sys_info)
> #endif
>
> #if defined(CONFIG_FSL_IFC)
> - ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
> -
> - sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> + sys_info->freq_localbus = sys_info->freq_systembus /
> + CONFIG_SYS_FSL_IFC_CLK_DIV;
> #endif
> }
>
>
After this change, sys_info->freq_localbus holds the input clock of
local bus, instead of output clock previously. It should be noted in the
commit message. Same comment goes to patch 3/5.
York
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