It also removes the qspi pin configuration done during the
board initialization.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
arch/arm/dts/stm32f746-disco.dts | 1 +
arch/arm/dts/stm32f746.dtsi | 11 ++++++++
board/st/stm32f746-disco/stm32f746-disco.c | 43 ------------------------------
3 files changed, 12 insertions(+), 43 deletions(-)
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 3d6002f..07e0ca7 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -93,6 +93,7 @@
};
&qspi {
+ pinctrl-0 = <&qspi_pins>;
status = "okay";
qflash0: n25q128a {
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 431e79c..b2b0b5f 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -131,6 +131,17 @@
slew-rate = <2>;
};
};
+ qspi_pins: qspi@0{
+ pins {
+ pinmux =
<STM32F746_PB2_FUNC_QUADSPI_CLK>,
+
<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+
<STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
+
<STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
+
<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
+
<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+ slew-rate = <2>;
+ };
+ };
};
};
};
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c
b/board/st/stm32f746-disco/stm32f746-disco.c
index 8343f82..fdad8d1 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -262,55 +262,12 @@ static int stmmac_setup(void)
#endif
#ifdef CONFIG_STM32_QSPI
-const struct stm32_gpio_ctl gpio_ctl_qspi_9 = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF9
-};
-
-const struct stm32_gpio_ctl gpio_ctl_qspi_10 = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF10
-};
-
-static const struct stm32_gpio_dsc qspi_af9_gpio[] = {
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */
-};
-
-static const struct stm32_gpio_dsc qspi_af10_gpio[] = {
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */
-};
static int qspi_setup(void)
{
- int res = 0;
- int i;
-
clock_setup(GPIO_B_CLOCK_CFG);
clock_setup(GPIO_D_CLOCK_CFG);
clock_setup(GPIO_E_CLOCK_CFG);
-
- for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) {
- res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9);
- if (res)
- return res;
- }
-
- for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) {
- res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10);
- if (res)
- return res;
- }
-
return 0;
}
#endif
--
1.9.1
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