On 30 January 2017 at 12:35, Maxim Sloyko <max...@google.com> wrote: > > Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. > Without this fix, valid setting can lead to division by zero > when requesting the rate of H-PLL or M-PLL clocks. > > Signed-off-by: Maxim Sloyko <max...@google.com>
Reviewed-by: Simon Glass <s...@chromium.org> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
