Hi. On 11.02.2017 16:08, Icenowy Zheng wrote: [..] > @@ -299,6 +190,13 @@ static void mctl_h3_zq_calibration_quirk(struct > dram_para *para) > { > struct sunxi_mctl_ctl_reg * const mctl_ctl = > (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; > + int zq_count; > + > +#if defined CONFIG_SUNXI_DRAM_DDR3 > + zq_count = 6;
This doesn't depend on DRAM type, but on how many ZQ calibration groups exist. H3 had three: AC, DX0/1 and DX2/3. Devices with only 16bit bus width most likely only have AC and DX0/1. > +#else > +#error Unsupported DRAM type! > +#endif > > if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && > (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { > @@ -327,7 +225,7 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para > *para) > > writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); > > - for (i = 0; i < 6; i++) { > + for (i = 0; i < zq_count; i++) { I think for (i = 0; i < (1 + (num_databyte_lanes / 2)) * 2; i++) would be the cleanest way of handling this, with num_databyte_lanes being chip-dependent. But, as the name of this function already states, this is a quirk for a bug in H3, which always has 4 databyte lanes. Are you sure other chips need this quirk too? H5 and A64 for example work well with 'normal' ZQ calibration. Jens > u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; > > writel((zq << 20) | (zq << 16) | (zq << 12) | > @@ -349,7 +247,9 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para > *para) > > writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); > writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); > +#if defined CONFIG_SUNXI_DRAM_DDR3 > writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); > +#endif > } > } > > @@ -358,7 +258,12 @@ static void mctl_set_cr(struct dram_para *para) > struct sunxi_mctl_com_reg * const mctl_com = > (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; > > - writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | > + writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_INTERLEAVED | > +#if defined CONFIG_SUNXI_DRAM_DDR3 > + MCTL_CR_DDR3 | > +#else > +#error Unsupported DRAM type! > +#endif > (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : > MCTL_CR_FOUR_BANKS) | > MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | > (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot