MMU tables should be flushed if current code runs with d-cache on. This
applies to early MMU tables with SPL boot, and all final MMU tables.
Signed-off-by: York Sun <york....@nxp.com>
---
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 800ad62..fcf8a75 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -80,6 +80,13 @@ static inline void early_mmu_setup(void)
/* Create early page tables */
setup_pgtables();
+
+#if defined(CONFIG_SPL) || !defined(CONFIG_SPL_BUILD)
+ /* For SPL RAM boot, cache is enabled. MMU table needs to be flushed */
+ flush_dcache_range(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+#endif
+
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
get_tcr(el, NULL, NULL) &
@@ -184,6 +191,8 @@ static inline void final_mmu_setup(void)
/* flush new MMU table */
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
+ flush_dcache_range(gd->arch.tlb_emerg,
+ gd->arch.tlb_emerg + gd->arch.tlb_size);
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
--
2.7.4
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