Sorry again, and with DDR2.
On Thu, Oct 22, 2009 at 11:42 AM, Werner Nedel <wmne...@gmail.com> wrote: > Hi, > > sorry about that. I'm working on a MPC8548 platform and using the mpc8xxx > common code for DDR configuration. > > > On Thu, Oct 22, 2009 at 11:36 AM, Kumar Gala <ga...@kernel.crashing.org>wrote: > >> >> On Oct 22, 2009, at 6:48 AM, Werner Nedel wrote: >> >> Hi, >>> >>> I was looking the ctrl_regs.c file at the last release of u-boot, >>> specifically at sdram_mode register, and checking at AN3369.pdf I think >>> that >>> Rtt bit position might be wrong. At the code, the bit shifting is 5, but >>> shouldn't be 6? I think that it overwrites AL register. >>> >> >> Can you be more specific about what arch/platform you are taking about. >> >> - k >> > >
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