Since commit ce412b7, RGMII TX clock internal delay is not enabled for
AR8033 unconditionally. On LS1021ATWR board, the third port eTSEC3 uses
AR8033 in RGMII mode. The TX/RX internal delay needs to be enabled.
This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
clock internal delay for AR8033 on the third port.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
board/freescale/ls1021atwr/ls1021atwr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index d96fd77..ff32d5c 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -273,6 +273,7 @@ int board_eth_init(bd_t *bis)
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
+ tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
#endif
if (!num) {
--
2.1.0.27.g96db324
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