On 04/26/2017 09:36 PM, Dinh Nguyen wrote:
The SMPEN bit is located in the cpuectlr_el1 register and not the
cpuactlr_el1 register. Adjust the comment accordingly and also fix
a spelling error.
Signed-off-by: Dinh Nguyen <[email protected]>
CC: Mingkai Hu <[email protected]>
CC: Gong Qianyu <[email protected]>
CC: Mateusz Kulikowski <[email protected]>
CC: Hou Zhiqiang <[email protected]>
CC: York Sun <[email protected]>
CC: Albert Aribaud <[email protected]>
CC: Masahiro Yamada <[email protected]>
---
arch/arm/cpu/armv8/start.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 62d97f7..354468b 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -86,12 +86,12 @@ save_boot_params_ret:
0:
/*
- * Enalbe SMPEN bit for coherency.
+ * Enable SMPEN bit for coherency.
* This register is not architectural but at the moment
* this bit should be set for A53/A57/A72.
*/
#ifdef CONFIG_ARMV8_SET_SMPEN
- mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
+ mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
orr x0, x0, #0x40
msr S3_1_c15_c2_1, x0
#endif
Thanks for fixing this.
Reviewed-by: York Sun <[email protected]>
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