commit 70ed869e broke fsl pcie end-point initialization.
Returning 0 is not correct. The function must return the first free
bus number for the next controller.
fsl_pci_init() must still be called and a bus allocated even if the
controller is an end-point.
Signed-off-by: Ed Swarthout <ed.swarth...@freescale.com>
---
This fixes the current breakage, but I don't think adding another
layer (fsl_pci_init_port) and parameter structure is all that helpful.
So now there is:
pci_init_board() -> fsl_pci_init_port() -> fsl_pci_init() ->
pciauto_setup_device()
with even less flexibility on setting up the inbound
and outbound windows.
drivers/pci/fsl_pci_init.c | 19 +++++--------------
1 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 8fbab68..db2cd4b 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -420,20 +420,6 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
pci = (ccsr_fsl_pci_t *) pci_info->regs;
- if (pcie_ep) {
- volatile pit_t *pi = &pci->pit[2];
-
- pci_setup_indirect(hose, (u32)&pci->cfg_addr,
- (u32)&pci->cfg_data);
- out_be32(&pi->pitar, 0);
- out_be32(&pi->piwbar, 0);
- out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
-
- fsl_pci_config_unlock(hose);
- return 0;
- }
-
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
@@ -464,6 +450,11 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+ if (pcie_ep) {
+ fsl_pci_config_unlock(hose);
+ hose->last_busno = hose->first_busno;
+ }
+
printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
hose->first_busno, hose->last_busno);
--
1.5.6.5
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