On Sun, Apr 30, 2017 at 2:57 PM, Daniel Schwierzeck <daniel.schwierz...@gmail.com> wrote: > From: Paul Burton <paul.bur...@imgtec.com> > > On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is > present. When there is no IOCU we need to writeback or invalidate the > data caches at appropriate points. Perform this cache maintenance in > the pch_gbe driver which is used on the MIPS Boston development board. > > Signed-off-by: Paul Burton <paul.bur...@imgtec.com> > Reviewed-by: Bin Meng <bmeng...@gmail.com> > Tested-by: Bin Meng <bmeng...@gmail.com> > Signed-off-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
