Hello Kever,
Am 15.06.2017 um 05:04 schrieb Kever Yang:
> Hi Wadim,
>
>
> On 06/13/2017 07:20 PM, Wadim Egorov wrote:
>> Sometimes it's helpful to know the reset reason caused in the SoC.
>> Add reset reason detection for the RK3288 SoC.
>> This will set an environemt variable which represents the reset reason.
>>
>> Signed-off-by: Wadim Egorov <w.ego...@phytec.de>
>> ---
>> arch/arm/mach-rockchip/rk3288-board.c | 28
>> ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm/mach-rockchip/rk3288-board.c
>> b/arch/arm/mach-rockchip/rk3288-board.c
>> index a354d99..8cdc7dc 100644
>> --- a/arch/arm/mach-rockchip/rk3288-board.c
>> +++ b/arch/arm/mach-rockchip/rk3288-board.c
>> @@ -11,6 +11,7 @@
>> #include <syscon.h>
>> #include <asm/io.h>
>> #include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3288.h>
>> #include <asm/arch/periph.h>
>> #include <asm/arch/pmu_rk3288.h>
>> #include <asm/arch/qos_rk3288.h>
>> @@ -70,10 +71,37 @@ int rk3288_qos_init(void)
>> return 0;
>> }
>> +static void rk3288_detect_reset_reason(void)
>> +{
>> + struct rk3288_cru *cru = rockchip_get_cru();
>> + if (IS_ERR(cru))
>> + return;
>> +
>> + switch (cru->cru_glb_rst_st) {
>> + case (1 << 0):
>> + setenv("reset_reason", "POR");
>
> From RK3288 TRM, the bit 0 set to 1 means "last hot reset is first
> global rst",
> I think this means a software reset somewhere with write to register
> CRU_GLB_SRST_FST_VALUE.
>
> Do you test with power on and this bit will be set?
You are right, this bit will be only set by triggering register
CRU_GLB_SRST_FST_VALUE or CRU_GLB_SRST_SND_VALUE. It's not a POR.
So bit 0 and 1 should set the reset_reason to RST.
Do you know if there is a way to detect a cold start? I think we can
assume a cold start if cru_glb_rst_st is 0.
Register cru_glb_rst_st can also have two or more bits set, for example:
mw 0xff7601b0 0xfffffdb9
followed by
mw 0xff7601b4 0xffffeca8
after a reset, will give us cru_glb_rst_st=3. Do you think it is ok to
clear cru_glb_rst_st after detecting the reset reason? So we can be sure
about the last reset cause.
Regards,
Wadim
>
> Thanks,
> - Kever
>> + break;
>> + case (1 << 1):
>> + setenv("reset_reason", "RST");
>> + break;
>> + case (1 << 2):
>> + case (1 << 3):
>> + setenv("reset_reason", "THERMAL");
>> + break;
>> + case (1 << 4):
>> + case (1 << 5):
>> + setenv("reset_reason", "WDOG");
>> + break;
>> + default:
>> + setenv("reset_reason", "unknown reset");
>> + }
>> +}
>> +
>> int board_late_init(void)
>> {
>> setup_boot_mode();
>> rk3288_qos_init();
>> + rk3288_detect_reset_reason();
>> return rk_board_late_init();
>> }
>
>
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