add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu <dave...@freescale.com>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++++++++++++++------
cpu/mpc8xxx/ddr/options.c | 1 +
include/asm-ppc/fsl_ddr_sdram.h | 5 +++++
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 2736006..5f0c611 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1004,8 +1004,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr,
unsigned int zq_en)
}
/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
-static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
- unsigned int wrlvl_en)
+static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
+ const memctl_options_t *popts)
{
/*
* First DQS pulse rising edge after margining mode
@@ -1032,8 +1032,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
/* tWL_DQSEN min = 25 nCK, we set it 32 */
wrlvl_dqsen = 0x5;
/*
- * Write leveling sample time at least need 14 clocks
- * due to tWLO = 9, we set it 15 clocks
+ * Write leveling sample time at least need 6 clocks
+ * higher than tWLO to allow enough time for progagation
+ * delay and sampling the prime data bits.
*/
wrlvl_smpl = 0xf;
/*
@@ -1046,9 +1047,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
* Write leveling start time
* The value use for the DQS_ADJUST for the first sample
* when write leveling is enabled.
- * we set it 1 clock delay
*/
wrlvl_start = 0x8;
+ /*
+ * Override the write leveling sample and start time
+ * according to specific board
+ */
+ if (popts->wrlvl_override) {
+ wrlvl_smpl = popts->wrlvl_sample;
+ wrlvl_start = popts->wrlvl_start;
+ }
}
ddr->ddr_wrlvl_cntl = (0
@@ -1334,7 +1342,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en);
- set_ddr_wrlvl_cntl(ddr, wrlvl_en);
+ set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
set_ddr_sr_cntr(ddr, sr_it);
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 26ac480..32ff12b 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int
all_DIMMs_registered,
* meet the tQDSS under different loading.
*/
popts->wrlvl_en = 1;
+ popts->wrlvl_override = 0;
#endif
/*
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 69b857b..d978d70 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -177,6 +177,11 @@ typedef struct memctl_options_s {
unsigned int clk_adjust; /* */
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+
+ unsigned int wrlvl_override;
+ unsigned int wrlvl_sample; /* Write leveling */
+ unsigned int wrlvl_start;
+
unsigned int half_strength_driver_enable;
unsigned int twoT_en;
unsigned int threeT_en;
--
1.5.6
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