From: Patrice Chotard <patrice.chot...@st.com>
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c
This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.
Signed-off-by: Patrice Chotard <patrice.chot...@st.com>
Reviewed-by: Vikas Manocha <vikas.mano...@st.com>
---
arch/arm/include/asm/arch-stm32f7/fmc.h | 74 ------------------------------
board/st/stm32f746-disco/stm32f746-disco.c | 1 -
drivers/ram/stm32_sdram.c | 59 +++++++++++++++++++++++-
3 files changed, 58 insertions(+), 76 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-stm32f7/fmc.h
diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h
b/arch/arm/include/asm/arch-stm32f7/fmc.h
deleted file mode 100644
index 4741e5a..0000000
--- a/arch/arm/include/asm/arch-stm32f7/fmc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2013
- * Pavel Boldin, Emcraft Systems, pabol...@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lu...@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _MACH_FMC_H_
-#define _MACH_FMC_H_
-
-struct stm32_fmc_regs {
- u32 sdcr1; /* Control register 1 */
- u32 sdcr2; /* Control register 2 */
- u32 sdtr1; /* Timing register 1 */
- u32 sdtr2; /* Timing register 2 */
- u32 sdcmr; /* Mode register */
- u32 sdrtr; /* Refresh timing register */
- u32 sdsr; /* Status register */
-};
-
-/*
- * FMC registers base
- */
-#define STM32_SDRAM_FMC ((struct stm32_fmc_regs
*)SDRAM_FMC_BASE)
-
-/* Control register SDCR */
-#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
-#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
-#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
-#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
-#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
-#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
-#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
-#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
-#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
-
-/* Timings register SDTR */
-#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
-#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
-#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
-#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
-#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
-#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
-#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
-
-
-#define FMC_SDCMR_NRFS_SHIFT 5
-
-#define FMC_SDCMR_MODE_NORMAL 0
-#define FMC_SDCMR_MODE_START_CLOCK 1
-#define FMC_SDCMR_MODE_PRECHARGE 2
-#define FMC_SDCMR_MODE_AUTOREFRESH 3
-#define FMC_SDCMR_MODE_WRITE_MODE 4
-#define FMC_SDCMR_MODE_SELFREFRESH 5
-#define FMC_SDCMR_MODE_POWERDOWN 6
-
-#define FMC_SDCMR_BANK_1 BIT(4)
-#define FMC_SDCMR_BANK_2 BIT(3)
-
-#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
-
-#define FMC_SDSR_BUSY BIT(5)
-
-#define FMC_BUSY_WAIT() do { \
- __asm__ __volatile__ ("dsb" : : : "memory"); \
- while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
- ; \
- } while (0)
-
-
-#endif /* _MACH_FMC_H_ */
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c
b/board/st/stm32f746-disco/stm32f746-disco.c
index fc4c60c..4314c71 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -13,7 +13,6 @@
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
#include <dm/platform_data/serial_stm32x7.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_defs.h>
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 902de2b..4146b9d 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -10,11 +10,68 @@
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
-#include <asm/arch/fmc.h>
#include <asm/arch/stm32.h>
DECLARE_GLOBAL_DATA_PTR;
+struct stm32_fmc_regs {
+ u32 sdcr1; /* Control register 1 */
+ u32 sdcr2; /* Control register 2 */
+ u32 sdtr1; /* Timing register 1 */
+ u32 sdtr2; /* Timing register 2 */
+ u32 sdcmr; /* Mode register */
+ u32 sdrtr; /* Refresh timing register */
+ u32 sdsr; /* Status register */
+};
+
+/*
+ * FMC registers base
+ */
+#define STM32_SDRAM_FMC ((struct stm32_fmc_regs
*)SDRAM_FMC_BASE)
+
+/* Control register SDCR */
+#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
+#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
+#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
+#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
+#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
+#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
+#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
+#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
+#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
+
+/* Timings register SDTR */
+#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
+#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
+#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
+#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
+#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
+#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
+#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
+
+#define FMC_SDCMR_NRFS_SHIFT 5
+
+#define FMC_SDCMR_MODE_NORMAL 0
+#define FMC_SDCMR_MODE_START_CLOCK 1
+#define FMC_SDCMR_MODE_PRECHARGE 2
+#define FMC_SDCMR_MODE_AUTOREFRESH 3
+#define FMC_SDCMR_MODE_WRITE_MODE 4
+#define FMC_SDCMR_MODE_SELFREFRESH 5
+#define FMC_SDCMR_MODE_POWERDOWN 6
+
+#define FMC_SDCMR_BANK_1 BIT(4)
+#define FMC_SDCMR_BANK_2 BIT(3)
+
+#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
+
+#define FMC_SDSR_BUSY BIT(5)
+
+#define FMC_BUSY_WAIT() do { \
+ __asm__ __volatile__ ("dsb" : : : "memory"); \
+ while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
+ ; \
+ } while (0)
+
struct stm32_sdram_control {
u8 no_columns;
u8 no_rows;
--
1.9.1
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