Hi Simon, On Wed, Jul 19, 2017 at 11:06 AM, Simon Glass <s...@chromium.org> wrote: > On 14 July 2017 at 05:55, Mario Six <mario....@gdsys.cc> wrote: >> Add a driver for the TX side of the Xilinx LogiCore DisplayPort IP core. >> >> Signed-off-by: Mario Six <mario....@gdsys.cc> >> --- >> >> drivers/transmitter/Kconfig | 6 + >> drivers/transmitter/Makefile | 1 + >> drivers/transmitter/logicore_dp_dpcd.h | 342 +++++ >> drivers/transmitter/logicore_dp_tx.c | 1984 >> ++++++++++++++++++++++++++++ >> drivers/transmitter/logicore_dp_tx.h | 40 + >> drivers/transmitter/logicore_dp_tx_regif.h | 365 +++++ >> 6 files changed, 2738 insertions(+) >> create mode 100644 drivers/transmitter/logicore_dp_dpcd.h >> create mode 100644 drivers/transmitter/logicore_dp_tx.c >> create mode 100644 drivers/transmitter/logicore_dp_tx.h >> create mode 100644 drivers/transmitter/logicore_dp_tx_regif.h > > Can we use UCLASS_DISPLAY? >
Yes, the display uclass should work; I'll move it there in v2. >> >> diff --git a/drivers/transmitter/Kconfig b/drivers/transmitter/Kconfig >> index 64ca08f8b8..e5613586a3 100644 >> --- a/drivers/transmitter/Kconfig >> +++ b/drivers/transmitter/Kconfig >> @@ -13,4 +13,10 @@ config SANDBOX_TRANSMITTER >> help >> Enable the dummy transmitter for the sandbox. >> >> +config LOGICORE_DP_TX >> + bool "Enable Logicore DP TX driver" >> + depends on DM > > DM_VIDEO? > As soon as it's move to the display uclass, naturally. :-) >> + help >> + Enabled the driver for the Logicore DP TX display port transmitter. > > Enable. Also can you expand this help to explain what it is? > I'll expand the help text a bit in v2. >> + >> endif >> diff --git a/drivers/transmitter/Makefile b/drivers/transmitter/Makefile >> index b873e63e28..088922d992 100644 >> --- a/drivers/transmitter/Makefile >> +++ b/drivers/transmitter/Makefile >> @@ -7,3 +7,4 @@ >> >> obj-y += transmitter-uclass.o >> obj-$(CONFIG_SANDBOX_TRANSMITTER) += sandbox_transmitter.o >> +obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o >> diff --git a/drivers/transmitter/logicore_dp_dpcd.h >> b/drivers/transmitter/logicore_dp_dpcd.h >> new file mode 100644 >> index 0000000000..6858294551 >> --- /dev/null >> +++ b/drivers/transmitter/logicore_dp_dpcd.h >> @@ -0,0 +1,342 @@ >> +/* >> + * logicore_dp_dpcd.h >> + * >> + * DPCD interface definition for XILINX LogiCore DisplayPort v6.1 >> + * based on Xilinx dp_v3_1 driver sources >> + * >> + * (C) Copyright 2016 >> + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eib...@gdsys.cc >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#ifndef __GDSYS_LOGICORE_DP_DPCD_H__ >> +#define __GDSYS_LOGICORE_DP_DPCD_H__ >> + >> +/* receiver capability field */ >> +#define DPCD_REV 0x00000 >> +#define DPCD_MAX_LINK_RATE 0x00001 >> +#define DPCD_MAX_LANE_COUNT 0x00002 >> +#define DPCD_MAX_DOWNSPREAD 0x00003 >> +#define DPCD_NORP_PWR_V_CAP 0x00004 >> +#define DPCD_DOWNSP_PRESENT 0x00005 >> +#define DPCD_ML_CH_CODING_CAP 0x00006 >> +#define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007 >> +#define DPCD_RX_PORT0_CAP_0 >> 0x00008 >> +#define DPCD_RX_PORT0_CAP_1 >> 0x00009 >> +#define DPCD_RX_PORT1_CAP_0 >> 0x0000A >> +#define DPCD_RX_PORT1_CAP_1 >> 0x0000B >> +#define DPCD_I2C_SPEED_CTL_CAP 0x0000C >> +#define DPCD_EDP_CFG_CAP 0x0000D >> +#define DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E >> +#define DPCD_ADAPTER_CAP 0x0000F >> +#define DPCD_FAUX_CAP 0x00020 >> +#define DPCD_MSTM_CAP 0x00021 >> +#define DPCD_NUM_AUDIO_EPS 0x00022 >> +#define DPCD_AV_GRANULARITY >> 0x00023 >> +#define DPCD_AUD_DEC_LAT_7_0 0x00024 >> +#define DPCD_AUD_DEC_LAT_15_8 0x00025 >> +#define DPCD_AUD_PP_LAT_7_0 0x00026 >> +#define DPCD_AUD_PP_LAT_15_8 0x00027 >> +#define DPCD_VID_INTER_LAT 0x00028 >> +#define DPCD_VID_PROG_LAT 0x00029 >> +#define DPCD_REP_LAT 0x0002A >> +#define DPCD_AUD_DEL_INS_7_0 0x0002B >> +#define DPCD_AUD_DEL_INS_15_8 0x0002C >> +#define DPCD_AUD_DEL_INS_23_16 0x0002D >> +#define DPCD_GUID 0x00030 >> +#define DPCD_RX_GTC_VALUE_7_0 0x00054 >> +#define DPCD_RX_GTC_VALUE_15_8 0x00055 >> +#define DPCD_RX_GTC_VALUE_23_16 >> 0x00056 >> +#define DPCD_RX_GTC_VALUE_31_24 >> 0x00057 >> +#define DPCD_RX_GTC_MSTR_REQ 0x00058 >> +#define DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059 >> +#define DPCD_DOWNSP_0_CAP 0x00080 >> +#define DPCD_DOWNSP_1_CAP 0x00081 >> +#define DPCD_DOWNSP_2_CAP 0x00082 >> +#define DPCD_DOWNSP_3_CAP 0x00083 >> +#define DPCD_DOWNSP_0_DET_CAP 0x00080 >> +#define DPCD_DOWNSP_1_DET_CAP 0x00084 >> +#define DPCD_DOWNSP_2_DET_CAP 0x00088 >> +#define DPCD_DOWNSP_3_DET_CAP 0x0008C >> + >> +/* link configuration field */ >> +#define DPCD_LINK_BW_SET 0x00100 >> +#define DPCD_LANE_COUNT_SET 0x00101 >> +#define DPCD_TP_SET 0x00102 >> +#define DPCD_TRAINING_LANE0_SET >> 0x00103 >> +#define DPCD_TRAINING_LANE1_SET >> 0x00104 >> +#define DPCD_TRAINING_LANE2_SET >> 0x00105 >> +#define DPCD_TRAINING_LANE3_SET >> 0x00106 >> +#define DPCD_DOWNSPREAD_CTRL 0x00107 >> +#define DPCD_ML_CH_CODING_SET 0x00108 >> +#define DPCD_I2C_SPEED_CTL_SET 0x00109 >> +#define DPCD_EDP_CFG_SET 0x0010A >> +#define DPCD_LINK_QUAL_LANE0_SET 0x0010B >> +#define DPCD_LINK_QUAL_LANE1_SET 0x0010C >> +#define DPCD_LINK_QUAL_LANE2_SET 0x0010D >> +#define DPCD_LINK_QUAL_LANE3_SET 0x0010E >> +#define DPCD_TRAINING_LANE0_1_SET2 0x0010F >> +#define DPCD_TRAINING_LANE2_3_SET2 0x00110 >> +#define DPCD_MSTM_CTRL 0x00111 >> +#define DPCD_AUDIO_DELAY_7_0 0x00112 >> +#define DPCD_AUDIO_DELAY_15_8 0x00113 >> +#define DPCD_AUDIO_DELAY_23_6 0x00114 >> +#define DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118 >> +#define DPCD_FAUX_MODE_CTRL 0x00120 >> +#define DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121 >> +#define DPCD_BACK_CH_STATUS 0x00122 >> +#define DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123 >> +#define DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME >> 0x00125 >> +#define DPCD_TX_GTC_VALUE_7_0 0x00154 >> +#define DPCD_TX_GTC_VALUE_15_8 0x00155 >> +#define DPCD_TX_GTC_VALUE_23_16 >> 0x00156 >> +#define DPCD_TX_GTC_VALUE_31_24 >> 0x00157 >> +#define DPCD_RX_GTC_VALUE_PHASE_SKEW_EN >> 0x00158 >> +#define DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159 >> +#define DPCD_ADAPTER_CTRL 0x001A0 >> +#define DPCD_BRANCH_DEVICE_CTRL >> 0x001A1 >> +#define DPCD_PAYLOAD_ALLOCATE_SET 0x001C0 >> +#define DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1 >> +#define DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2 >> + >> +/* link/sink status field */ >> +#define DPCD_SINK_COUNT >> 0x00200 >> +#define DPCD_DEVICE_SERVICE_IRQ >> 0x00201 >> +#define DPCD_STATUS_LANE_0_1 0x00202 >> +#define DPCD_STATUS_LANE_2_3 0x00203 >> +#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204 >> +#define DPCD_SINK_STATUS 0x00205 >> +#define DPCD_ADJ_REQ_LANE_0_1 0x00206 >> +#define DPCD_ADJ_REQ_LANE_2_3 0x00207 >> +#define DPCD_TRAINING_SCORE_LANE_0 0x00208 >> +#define DPCD_TRAINING_SCORE_LANE_1 0x00209 >> +#define DPCD_TRAINING_SCORE_LANE_2 0x0020A >> +#define DPCD_TRAINING_SCORE_LANE_3 0x0020B >> +#define DPCD_ADJ_REQ_PC2 0x0020C >> +#define DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT >> 0x0020D >> +#define DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210 >> +#define DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212 >> +#define DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214 >> +#define DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216 >> + >> +/* automated testing sub-field */ >> +#define DPCD_FAUX_FORWARD_CH_STATUS 0x00280 >> +#define DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281 >> +#define DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282 >> +#define DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0 >> +#define DPCD_VC_PAYLOAD_ID_SLOT(SlotNum) \ >> + (DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum) >> + >> +/* sink control field */ >> +#define DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 >> + >> +/* sideband message buffers */ >> +#define DPCD_DOWN_REQ 0x01000 >> +#define DPCD_UP_REP 0x01200 >> +#define DPCD_DOWN_REP 0x01400 >> +#define DPCD_UP_REQ 0x01600 >> + >> +/* event status indicator field */ >> +#define DPCD_SINK_COUNT_ESI 0x02002 >> +#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003 >> +#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004 >> +#define DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005 >> +#define DPCD_SINK_LANE0_1_STATUS 0x0200C >> +#define DPCD_SINK_LANE2_3_STATUS 0x0200D >> +#define DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E >> +#define DPCD_SINK_STATUS_ESI 0x0200F >> + >> +/* >> + * field addresses and sizes. >> + */ >> +#define DPCD_RECEIVER_CAP_FIELD_START DPCD_REV >> +#define DPCD_RECEIVER_CAP_FIELD_SIZE 0x100 >> +#define DPCD_LINK_CFG_FIELD_START DPCD_LINK_BW_SET >> +#define DPCD_LINK_CFG_FIELD_SIZE 0x100 >> +#define DPCD_LINK_SINK_STATUS_FIELD_START DPCD_SINK_COUNT >> +#define DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17 >> +/* 0x00000: DPCD_REV */ >> +#define DPCD_REV_MNR_MASK 0x0F >> +#define DPCD_REV_MJR_MASK 0xF0 >> +#define DPCD_REV_MJR_SHIFT 4 >> +/* 0x00001: MAX_LINK_RATE */ >> +#define DPCD_MAX_LINK_RATE_162GBPS 0x06 >> +#define DPCD_MAX_LINK_RATE_270GBPS 0x0A >> +#define DPCD_MAX_LINK_RATE_540GBPS 0x14 >> +/* 0x00002: MAX_LANE_COUNT */ >> +#define DPCD_MAX_LANE_COUNT_MASK 0x1F >> +#define DPCD_MAX_LANE_COUNT_1 0x01 >> +#define DPCD_MAX_LANE_COUNT_2 0x02 >> +#define DPCD_MAX_LANE_COUNT_4 0x04 >> +#define DPCD_TPS3_SUPPORT_MASK 0x40 >> +#define DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 >> +/* 0x00003: MAX_DOWNSPREAD */ >> +#define DPCD_MAX_DOWNSPREAD_MASK 0x01 >> +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40 >> +/* 0x00005: DOWNSP_PRESENT */ >> +#define DPCD_DOWNSP_PRESENT_MASK 0x01 >> +#define DPCD_DOWNSP_TYPE_MASK 0x06 >> +#define DPCD_DOWNSP_TYPE_SHIFT 1 >> +#define DPCD_DOWNSP_TYPE_DP 0x0 >> +#define DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1 >> +#define DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2 >> +#define DPCD_DOWNSP_TYPE_OTHERS 0x3 >> +#define DPCD_DOWNSP_FORMAT_CONV_MASK 0x08 >> +#define DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10 >> +/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */ >> +#define DPCD_ML_CH_CODING_MASK 0x01 >> +/* 0x00007: DOWNSP_COUNT_MSA_OUI */ >> +#define DPCD_DOWNSP_COUNT_MASK 0x0F >> +#define DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40 >> +#define DPCD_OUI_SUPPORT_MASK 0x80 >> +/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */ >> +#define DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02 >> +#define DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04 >> +/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */ >> +#define DPCD_I2C_SPEED_CTL_NONE 0x00 >> +#define DPCD_I2C_SPEED_CTL_1KBIPS 0x01 >> +#define DPCD_I2C_SPEED_CTL_5KBIPS 0x02 >> +#define DPCD_I2C_SPEED_CTL_10KBIPS 0x04 >> +#define DPCD_I2C_SPEED_CTL_100KBIPS 0x08 >> +#define DPCD_I2C_SPEED_CTL_400KBIPS 0x10 >> +#define DPCD_I2C_SPEED_CTL_1MBIPS 0x20 >> +/* 0x0000E: TRAIN_AUX_RD_INTERVAL */ >> +#define DPCD_TRAIN_AUX_RD_INT_100_400US 0x00 >> +#define DPCD_TRAIN_AUX_RD_INT_4MS 0x01 >> +#define DPCD_TRAIN_AUX_RD_INT_8MS 0x02 >> +#define DPCD_TRAIN_AUX_RD_INT_12MS 0x03 >> +#define DPCD_TRAIN_AUX_RD_INT_16MS 0x04 >> +/* 0x00020: DPCD_FAUX_CAP */ >> +#define DPCD_FAUX_CAP_MASK 0x01 >> +/* 0x00021: MSTM_CAP */ >> +#define DPCD_MST_CAP_MASK 0x01 >> +/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */ >> +#define DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07 >> +#define DPCD_DOWNSP_X_CAP_TYPE_DP 0x0 >> +#define DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1 >> +#define DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2 >> +#define DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3 >> +#define DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4 >> +#define DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5 >> +#define DPCD_DOWNSP_X_CAP_HPD_MASK 0x80 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5 >> +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7 >> +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ >> +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03 >> +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0 >> +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1 >> +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2 >> +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3 >> +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ >> +#define DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01 >> +#define DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02 >> +#define DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04 >> + >> +/* link configuration field masks, shifts, and register values */ >> +/* 0x00100: DPCD_LINK_BW_SET */ >> +#define DPCD_LINK_BW_SET_162GBPS 0x06 >> +#define DPCD_LINK_BW_SET_270GBPS 0x0A >> +#define DPCD_LINK_BW_SET_540GBPS 0x14 >> +/* 0x00101: LANE_COUNT_SET */ >> +#define DPCD_LANE_COUNT_SET_MASK 0x1F >> +#define DPCD_LANE_COUNT_SET_1 0x01 >> +#define DPCD_LANE_COUNT_SET_2 0x02 >> +#define DPCD_LANE_COUNT_SET_4 0x04 >> +#define DPCD_ENHANCED_FRAME_EN_MASK 0x80 >> +/* 0x00102: TP_SET */ >> +#define DPCD_TP_SEL_MASK 0x03 >> +#define DPCD_TP_SEL_OFF 0x0 >> +#define DPCD_TP_SEL_TP1 0x1 >> +#define DPCD_TP_SEL_TP2 0x2 >> +#define DPCD_TP_SEL_TP3 0x3 >> +#define DPCD_TP_SET_LQP_MASK 0x06 >> +#define DPCD_TP_SET_LQP_SHIFT 2 >> +#define DPCD_TP_SET_LQP_OFF 0x0 >> +#define DPCD_TP_SET_LQP_D102_TEST 0x1 >> +#define DPCD_TP_SET_LQP_SER_MES 0x2 >> +#define DPCD_TP_SET_LQP_PRBS7 0x3 >> +#define DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10 >> +#define DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 >> +#define DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0 >> +#define DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6 >> +#define DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0 >> +#define DPCD_TP_SET_SE_COUNT_SEL_DE 0x1 >> +#define DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2 >> +/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */ >> +#define DPCD_TRAINING_LANEX_SET_VS_MASK 0x03 >> +#define DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 >> +#define DPCD_TRAINING_LANEX_SET_PE_MASK 0x18 >> +#define DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 >> +#define DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 >> +/* 0x00107: DOWNSPREAD_CTRL */ >> +#define DPCD_SPREAD_AMP_MASK 0x10 >> +#define DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80 >> +/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */ >> +/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */ >> +/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */ >> +#define DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03 >> +#define DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04 >> +#define DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30 >> +#define DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4 >> +#define DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40 >> +/* 0x00111: MSTM_CTRL */ >> +#define DPCD_MST_EN_MASK 0x01 >> +#define DPCD_UP_REQ_EN_MASK 0x02 >> +#define DPCD_UP_IS_SRC_MASK 0x03 >> + >> +/* link/sink status field masks, shifts, and register values */ >> +/* 0x00200: SINK_COUNT */ >> +#define DPCD_SINK_COUNT_LOW_MASK 0x3F >> +#define DPCD_SINK_CP_READY_MASK 0x40 >> +#define DPCD_SINK_COUNT_HIGH_MASK 0x80 >> +#define DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1 >> +/* 0x00202: STATUS_LANE_0_1 */ >> +#define DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 >> +#define DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 >> +#define DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 >> +#define DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 >> +#define DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 >> +#define DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 >> +/* 0x00202: STATUS_LANE_2_3 */ >> +#define DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01 >> +#define DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02 >> +#define DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04 >> +#define DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10 >> +#define DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20 >> +#define DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40 >> +/* 0x00204: LANE_ALIGN_STATUS_UPDATED */ >> +#define DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \ >> + 0x01 >> +#define DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \ >> + 0x40 >> +#define DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \ >> + 0x80 >> +/* 0x00205: SINK_STATUS */ >> +#define DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01 >> +#define DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02 >> + >> +/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */ >> +#define DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 >> +#define DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C >> +#define DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 >> +#define DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 >> +#define DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 >> +#define DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 >> +#define DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 >> +/* 0x0020C: ADJ_REQ_PC2 */ >> +#define DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03 >> +#define DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C >> +#define DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2 >> +#define DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30 >> +#define DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4 >> +#define DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0 >> +#define DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6 >> + >> +#endif /* __GDSYS_LOGICORE_DP_DPCD_H__ */ >> diff --git a/drivers/transmitter/logicore_dp_tx.c >> b/drivers/transmitter/logicore_dp_tx.c >> new file mode 100644 >> index 0000000000..b61159cd89 >> --- /dev/null >> +++ b/drivers/transmitter/logicore_dp_tx.c >> @@ -0,0 +1,1984 @@ >> +/* >> + * logicore_dp_tx.c >> + * >> + * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source) >> + * based on Xilinx dp_v3_1 driver sources, updated to dp_v4_0 >> + * >> + * (C) Copyright 2016 >> + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eib...@gdsys.cc >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <clk.h> >> +#include <dm.h> >> +#include <errno.h> >> +#include <transmitter.h> >> + >> +#include "ihs_axi.h" >> + >> +#include "logicore_dp_dpcd.h" >> +#include "logicore_dp_tx_regif.h" >> +#include "logicore_dp_tx.h" >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +#define S_AXI_CLK_DEFAULT 100000000 >> + >> +#define PHY_CLOCK_SELECT_DEFAULT PHY_CLOCK_SELECT_540GBPS >> + >> +/* The maximum voltage swing level is 3. */ >> +#define MAXIMUM_VS_LEVEL 3 >> +/* The maximum pre-emphasis level is 3. */ >> +#define MAXIMUM_PE_LEVEL 3 >> + >> +/* Error out if an AUX request yields a defer reply more than 50 times. */ >> +#define AUX_MAX_DEFER_COUNT 50 >> +/* Error out if an AUX request times out more than 50 times awaiting a >> reply. */ >> +#define AUX_MAX_TIMEOUT_COUNT 50 >> +/* Error out if checking for a connected device times out more than 50 >> times. */ >> +#define IS_CONNECTED_MAX_TIMEOUT_COUNT 50 >> + >> +enum { >> + TS_CLOCK_RECOVERY, >> + TS_CHANNEL_EQUALIZATION, >> + TS_ADJUST_LINK_RATE, >> + TS_ADJUST_LANE_COUNT, >> + TS_FAILURE, >> + TS_SUCCESS >> +}; >> + >> +struct aux_transaction { >> + u16 cmd_code; >> + u8 num_bytes; >> + u32 address; >> + u8 *data; > > Comment these members. > OK, will add comments in v2. >> +}; >> + >> +/* >> + * all porch parameters have been removed because our videodata is >> hstart/vstart >> + * based and there is no benefit in keeping the porches >> + */ >> + >> +struct main_stream_attributes { >> + /* Pixel clock of the stream (in Hz). */ >> + u32 pixel_clock_hz; >> + /* Miscellaneous stream attributes 0 as specified by the DisplayPort >> + * 1.2 specification. >> + */ >> + u32 misc_0; >> + /* Miscellaneous stream attributes 1 as specified by the DisplayPort >> + * 1.2 specification. >> + */ >> + u32 misc_1; >> + /* N value for the video stream. */ >> + u32 n_vid; >> + /* M value used to recover the video clock from the link clock. */ >> + u32 m_vid; >> + /* Width of the user data input port. */ >> + u32 user_pixel_width; >> + /* Used to translate the number of pixels per line to the native >> + * internal 16-bit datapath. >> + */ >> + u32 data_per_lane; >> + /* Average number of bytes per transfer unit, scaled up by a factor >> of >> + * 1000. >> + */ >> + u32 avg_bytes_per_tu; >> + /* Size of the transfer unit in the framing logic. In MST mode, this >> is >> + * also the number of time slots that are alloted in the payload ID >> + * table. >> + */ >> + u32 transfer_unit_size; >> + /* Number of initial wait cycles at the start of a new line by the >> + * framing logic. >> + */ >> + u32 init_wait; >> + /* Bits per color component. */ >> + u32 bits_per_color; >> + /* The component format currently in use by the video stream. */ >> + u8 component_format; >> + /* The dynamic range currently in use by the video stream. */ >> + u8 dynamic_range; >> + /* The YCbCr colorimetry currently in use by the video stream. */ >> + u8 y_cb_cr_colorimetry; >> + /* Synchronous clock mode is currently in use by the video stream. */ >> + u8 synchronous_clock_mode; >> + /* If set to 1, the value stored for user_pixel_width will be used as >> + * the pixel width. >> + */ >> + u8 override_user_pixel_width; >> + /* Horiz. blank start (pixels). */ >> + u32 h_start; >> + /* Horiz. active resolution (pixels) */ >> + u16 h_active; >> + /* Horiz. sync width (pixels) */ >> + u16 h_sync_width; >> + /* Horiz. total (pixels) */ >> + u16 h_total; >> + /* Horiz. sync polarity (0=neg|1=pos) */ >> + bool h_sync_polarity; >> + /* Vert. blank start (in lines). */ >> + u32 v_start; >> + /* Vert. active resolution (lines) */ >> + u16 v_active; >> + /* Vert. sync width (lines) */ >> + u16 v_sync_width; >> + /* Vert. total (lines) */ >> + u16 v_total; >> + /* Vert. sync polarity (0=neg|1=pos) */ >> + bool v_sync_polarity; >> +}; >> + >> +struct link_config { >> + u8 lane_count; >> + u8 link_rate; >> + bool scrambler_en; >> + bool enhanced_framing_mode; >> + bool downspread_control; >> + u8 max_lane_count; >> + u8 max_link_rate; >> + bool support_enhanced_framing_mode; >> + bool support_downspread_control; >> + u8 vs_level; /* voltage swing for each lane */ >> + u8 pe_level; /* pre-emphasis/cursor level for each lane */ >> + u8 pattern; >> +}; >> + >> +struct dp_tx { >> + u32 base; >> + >> + u32 s_axi_clk; >> + >> + bool train_adaptive; >> + >> + u8 max_link_rate; >> + u8 max_lane_count; >> + >> + u8 dpcd_rx_caps[16]; >> + >> + /* This is a raw read of the RX device's status registers. The first >> 4 >> + * bytes correspond to the lane status associated with clock >> recovery, >> + * channel equalization, symbol lock, and interlane alignment. The >> + * remaining 2 bytes represent the pre-emphasis and voltage swing >> level >> + * adjustments requested by the RX device. >> + */ >> + u8 lane_status_ajd_reqs[6]; >> + >> + struct link_config link_config; >> + struct main_stream_attributes main_stream_attributes; >> +}; >> + >> +/* >> + * internal API >> + */ >> + >> +static u32 get_reg(struct udevice *dev, u32 reg) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + u32 value = 0; >> + int res; >> + >> + // TODO error handling > > /* TODO(email): Error handling > > (or do you intend to do in v2?) > I might as well fix it, since I'll have to tweak the methods again for the uclass move anyway. Will be fixed in v2. >> + res = axi_read(dev->parent, dp_tx->base + reg, &value); >> + if (res < 0) >> + printf("%s() failed; res = %d\n", __func__, res); > > How about debug() and return an error? > OK, I'll return the error from the axi_read in v2. >> + >> + return value; >> +} >> + >> +static void set_reg(struct udevice *dev, u32 reg, u32 value) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + >> + axi_write(dev->parent, dp_tx->base + reg, value); > > Can this fail? Error checking? > The function itself returns a error code, but I think it can't really fail in practice. Will check, and add error handling in v2 if necessary. >> +} >> + >> +/* >> + * Check if there is a connected RX device. >> + * The Xilinx original calls msleep_interruptible at least once, >> + * ignoring status. >> + */ >> +bool is_connected(struct udevice *dev) >> +{ >> + u8 retries = 0; >> + >> + do { >> + int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) & >> + INTERRUPT_SIG_STATE_HPD_STATE_MASK; >> + if (status) >> + return true; >> + >> + udelay(1000); >> + } while (retries++ < IS_CONNECTED_MAX_TIMEOUT_COUNT); >> + >> + return false; >> +} >> + >> +/* >> + * Wait for the DisplayPort PHY to come out of reset. >> + */ >> +static int wait_phy_ready(struct udevice *dev, u32 mask) >> +{ >> + u16 timeout = 20000; >> + u32 phy_status; >> + >> + /* Wait until the PHY is ready. */ >> + do { >> + phy_status = get_reg(dev, REG_PHY_STATUS) & mask; >> + >> + /* Protect against an infinite loop. */ >> + if (!timeout--) >> + return -ETIMEDOUT; >> + >> + udelay(20); >> + } while (phy_status != mask); >> + >> + return 0; >> +} >> + >> +/* AUX channel access */ >> + >> +/* >> + * Wait until another request is no longer in progress. >> + */ >> +static int aux_wait_ready(struct udevice *dev) >> +{ >> + int status; >> + u32 timeout = 100; >> + >> + /* Wait until the DisplayPort TX core is ready. */ >> + do { >> + status = get_reg(dev, REG_INTERRUPT_SIG_STATE); >> + >> + /* Protect against an infinite loop. */ >> + if (!timeout--) >> + return -ETIMEDOUT; >> + udelay(20); >> + } while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK); >> + >> + return 0; >> +} >> + >> +/* >> + * Wait for a reply indicating that the most recent AUX request >> + * has been received by the RX device. >> + */ >> +static int aux_wait_reply(struct udevice *dev) >> +{ >> + u32 timeout = 100; >> + >> + while (timeout > 0) { >> + int status = get_reg(dev, REG_REPLY_STATUS); >> + >> + /* Check for error. */ >> + if (status & REPLY_STATUS_REPLY_ERROR_MASK) >> + return -ETIMEDOUT; >> + >> + /* Check for a reply. */ >> + if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) && >> + !(status & >> + REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) && >> + !(status & >> + REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) { >> + return 0; >> + } >> + >> + timeout--; >> + udelay(20); > > This makes me think we should have a way to do us timeouts. > > We have get_timer(), so: > > start = get_timer(0); > ... > while () { > ... > if (get_timer(start) > 20) { > debug(...) > return -ETIMEDOUT; > } > > Perhaps we should have a timer_get_us_base(ulong base) which works in > a similar way? > That would indeed be helpful; I know that we use loops like this all over the place in our board code, so optimizing that would help a lot. >> + } >> + >> + return -ETIMEDOUT; >> +} >> + >> +/* >> + * Submit the supplied AUX request to the RX device over the AUX >> + * channel by writing the command, the destination address, (the write >> buffer >> + * for write commands), and the data size to the DisplayPort TX core. >> + */ >> +static int aux_request_send(struct udevice *dev, >> + struct aux_transaction *request) >> +{ >> + u32 timeout_count; >> + int status; >> + u8 index; >> + >> + /* Ensure that any pending AUX transactions have completed. */ >> + timeout_count = 0; >> + do { >> + status = get_reg(dev, REG_REPLY_STATUS); >> + >> + udelay(20); >> + timeout_count++; >> + if (timeout_count >= AUX_MAX_TIMEOUT_COUNT) >> + return -ETIMEDOUT; >> + } while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) || >> + (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK)); >> + >> + set_reg(dev, REG_AUX_ADDRESS, request->address); >> + >> + if ((request->cmd_code == AUX_CMD_WRITE) || >> + (request->cmd_code == AUX_CMD_I2C_WRITE) || >> + (request->cmd_code == AUX_CMD_I2C_WRITE_MOT)) { >> + /* Feed write data into the DisplayPort TX core's write >> FIFO. */ >> + for (index = 0; index < request->num_bytes; index++) { >> + set_reg(dev, >> + REG_AUX_WRITE_FIFO, request->data[index]); >> + } >> + } >> + >> + /* Submit the command and the data size. */ >> + set_reg(dev, REG_AUX_CMD, >> + ((request->cmd_code << AUX_CMD_SHIFT) | >> + ((request->num_bytes - 1) & >> + AUX_CMD_NBYTES_TRANSFER_MASK))); >> + >> + /* Check for a reply from the RX device to the submitted request. */ >> + status = aux_wait_reply(dev); >> + if (status) >> + /* Waiting for a reply timed out. */ >> + return -ETIMEDOUT; >> + >> + /* Analyze the reply. */ >> + status = get_reg(dev, REG_AUX_REPLY_CODE); >> + if ((status == AUX_REPLY_CODE_DEFER) || >> + (status == AUX_REPLY_CODE_I2C_DEFER)) { >> + /* The request was deferred. */ >> + return -EAGAIN; >> + } else if ((status == AUX_REPLY_CODE_NACK) || >> + (status == AUX_REPLY_CODE_I2C_NACK)) { >> + /* The request was not acknowledged. */ >> + return -EIO; >> + } >> + >> + /* The request was acknowledged. */ >> + >> + if ((request->cmd_code == AUX_CMD_READ) || >> + (request->cmd_code == AUX_CMD_I2C_READ) || >> + (request->cmd_code == AUX_CMD_I2C_READ_MOT)) { >> + /* Wait until all data has been received. */ >> + timeout_count = 0; >> + do { >> + status = get_reg(dev, REG_REPLY_DATA_COUNT); >> + >> + udelay(100); >> + timeout_count++; >> + if (timeout_count >= AUX_MAX_TIMEOUT_COUNT) >> + return -ETIMEDOUT; >> + } while (status != request->num_bytes); >> + >> + /* Obtain the read data from the reply FIFO. */ >> + for (index = 0; index < request->num_bytes; index++) >> + request->data[index] = get_reg(dev, >> REG_AUX_REPLY_DATA); >> + } >> + >> + return 0; >> +} >> + >> +/* >> + * Submit the supplied AUX request to the RX device over the AUX >> + * channel. If waiting for a reply times out, or if the DisplayPort TX core >> + * indicates that the request was deferred, the request is sent again (up >> to a >> + * maximum specified by AUX_MAX_DEFER_COUNT|AUX_MAX_TIMEOUT_COUNT). >> + */ >> +static int aux_request(struct udevice *dev, struct aux_transaction *request) >> +{ >> + u32 defer_count = 0; >> + u32 timeout_count = 0; >> + >> + while ((defer_count < AUX_MAX_DEFER_COUNT) && >> + (timeout_count < AUX_MAX_TIMEOUT_COUNT)) { >> + int status = aux_wait_ready(dev); >> + >> + if (status) { >> + /* The RX device isn't ready yet. */ >> + timeout_count++; >> + continue; >> + } >> + >> + status = aux_request_send(dev, request); >> + if (status == -EAGAIN) { >> + /* The request was deferred. */ >> + defer_count++; >> + } else if (status == -ETIMEDOUT) { >> + /* Waiting for a reply timed out. */ >> + timeout_count++; >> + } else { >> + /* -EIO indicates that the request was NACK'ed, >> + * 0 indicates that the request was ACK'ed. >> + */ >> + return status; >> + } >> + >> + udelay(100); >> + } >> + >> + /* The request was not successfully received by the RX device. */ >> + return -ETIMEDOUT; >> +} >> + >> +/* >> + * Common sequence of submitting an AUX command for >> + * AUX read, AUX write, I2C-over-AUX read, and I2C-over-AUX write >> transactions. >> + * If required, the reads and writes are split into multiple requests, each >> + * acting on a maximum of 16 bytes. >> + */ >> +static int aux_common(struct udevice *dev, u32 cmd_type, u32 address, >> + u32 num_bytes, u8 *data) >> +{ >> + struct aux_transaction request; >> + u32 bytes_left; >> + >> + /* >> + * set the start address for AUX transactions. For I2C transactions, >> + * this is the address of the I2C bus. >> + */ >> + request.address = address; >> + >> + bytes_left = num_bytes; >> + while (bytes_left) { >> + int status; >> + >> + request.cmd_code = cmd_type; >> + >> + if ((cmd_type == AUX_CMD_READ) || >> + (cmd_type == AUX_CMD_WRITE)) { >> + /* Increment address for normal AUX transactions. */ >> + request.address = address + (num_bytes - bytes_left); >> + } >> + >> + /* Increment the pointer to the supplied data buffer. */ >> + request.data = &data[num_bytes - bytes_left]; >> + >> + request.num_bytes = (bytes_left > 16) ? 16 : bytes_left; >> + bytes_left -= request.num_bytes; >> + >> + if ((cmd_type == AUX_CMD_I2C_READ) && bytes_left) { >> + /* Middle of a transaction I2C read request. Override >> + * the command code that was set to cmd_type. >> + */ >> + request.cmd_code = AUX_CMD_I2C_READ_MOT; >> + } else if ((cmd_type == AUX_CMD_I2C_WRITE) && bytes_left) { >> + /* Middle of a transaction I2C write request. >> Override >> + * the command code that was set to cmd_type. >> + */ >> + request.cmd_code = AUX_CMD_I2C_WRITE_MOT; >> + } >> + >> + status = aux_request(dev, &request); >> + if (status) >> + return status; >> + } >> + >> + return 0; >> +} >> + >> +/* >> + * Issue a read request over the AUX channel that will read from >> + * the RX device's DisplayPort Configuration data (DPCD) address space. The >> read >> + * message will be divided into multiple transactions which read a maximum >> of 16 >> + * bytes each. >> + */ >> +static int aux_read(struct udevice *dev, u32 dpcd_address, u32 >> bytes_to_read, >> + void *read_data) >> +{ >> + int status; >> + >> + if (!is_connected(dev)) >> + return -ENODEV; > > Can we use -ENXIO for this? That error means there is no device. There > is a device, it just isn't connected / working. > OK, will change in v2. >> + >> + /* Send AUX read transaction. */ >> + status = aux_common(dev, AUX_CMD_READ, dpcd_address, >> + bytes_to_read, (u8 *)read_data); >> + >> + return status; >> +} >> + >> +/* >> + * Issue a write request over the AUX channel that will write to >> + * the RX device's DisplayPort Configuration data (DPCD) address space. The >> + * write message will be divided into multiple transactions which write a >> + * maximum of 16 bytes each. >> + */ >> +static int aux_write(struct udevice *dev, u32 dpcd_address, u32 >> bytes_to_write, >> + void *write_data) >> +{ >> + int status; >> + >> + if (!is_connected(dev)) >> + return -ENODEV; > > Here too > Dito, will change in v2. >> + >> + /* Send AUX write transaction. */ >> + status = aux_common(dev, AUX_CMD_WRITE, dpcd_address, >> + bytes_to_write, (u8 *)write_data); >> + >> + return status; >> +} >> + >> +/* core initialization */ >> + >> +static int initialize(struct udevice *dev) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + u32 val; >> + u32 phy_config; >> + unsigned int k; >> + >> + /* place the PHY (and GTTXRESET) into reset. */ >> + phy_config = get_reg(dev, REG_PHY_CONFIG); >> + set_reg(dev, REG_PHY_CONFIG, phy_config | >> PHY_CONFIG_GT_ALL_RESET_MASK); >> + >> + /* reset the video streams and AUX logic. */ >> + set_reg(dev, REG_SOFT_RESET, >> + SOFT_RESET_VIDEO_STREAM_ALL_MASK | >> + SOFT_RESET_AUX_MASK); >> + >> + /* disable the DisplayPort TX core. */ >> + set_reg(dev, REG_ENABLE, 0); >> + >> + /* set the clock divider. */ >> + val = get_reg(dev, REG_AUX_CLK_DIVIDER); >> + val &= ~AUX_CLK_DIVIDER_VAL_MASK; >> + val |= dp_tx->s_axi_clk / 1000000; >> + set_reg(dev, REG_AUX_CLK_DIVIDER, val); >> + >> + /* set the DisplayPort TX core's clock speed. */ >> + set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT); >> + >> + /* bring the PHY (and GTTXRESET) out of reset. */ >> + set_reg(dev, REG_PHY_CONFIG, >> + phy_config & ~PHY_CONFIG_GT_ALL_RESET_MASK); >> + >> + /* enable the DisplayPort TX core. */ >> + set_reg(dev, REG_ENABLE, 1); >> + >> + /* Unmask Hot-Plug-Detect (HPD) interrupts. */ >> + set_reg(dev, REG_INTERRUPT_MASK, >> + ~INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK & >> + ~INTERRUPT_MASK_HPD_EVENT_MASK & >> + ~INTERRUPT_MASK_HPD_IRQ_MASK); >> + >> + for (k = 0; k < 4; k++) { >> + /* Disable pre-cursor levels. */ >> + set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0); >> + >> + /* Write default voltage swing levels to the TX registers. */ >> + set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0); >> + >> + /* Write default pre-emphasis levels to the TX registers. */ >> + set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0); >> + } >> + >> + return 0; >> +} >> + >> +bool is_link_rate_valid(struct udevice *dev, u8 link_rate) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + bool valid = true; >> + >> + if ((link_rate != LINK_BW_SET_162GBPS) && >> + (link_rate != LINK_BW_SET_270GBPS) && >> + (link_rate != LINK_BW_SET_540GBPS)) >> + valid = false; >> + else if (link_rate > dp_tx->link_config.max_link_rate) >> + valid = false; >> + >> + return valid; >> +} >> + >> +bool is_lane_count_valid(struct udevice *dev, u8 lane_count) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + bool valid = true; >> + >> + if ((lane_count != LANE_COUNT_SET_1) && >> + (lane_count != LANE_COUNT_SET_2) && >> + (lane_count != LANE_COUNT_SET_4)) >> + valid = false; >> + else if (lane_count > dp_tx->link_config.max_lane_count) >> + valid = false; >> + >> + return valid; >> +} >> + >> +static int get_rx_capabilities(struct udevice *dev) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + int status; >> + u8 rx_max_link_rate; >> + u8 rx_max_lane_count; >> + >> + if (!is_connected(dev)) >> + return -ENODEV; >> + >> + status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16, >> + dp_tx->dpcd_rx_caps); >> + if (status) >> + return -EIO; >> + >> + rx_max_link_rate = dp_tx->dpcd_rx_caps[DPCD_MAX_LINK_RATE]; >> + rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & >> + DPCD_MAX_LANE_COUNT_MASK; >> + >> + dp_tx->link_config.max_link_rate = >> + (rx_max_link_rate > dp_tx->max_link_rate) ? >> + dp_tx->max_link_rate : rx_max_link_rate; >> + if (!is_link_rate_valid(dev, rx_max_link_rate)) >> + return -EINVAL; >> + >> + dp_tx->link_config.max_lane_count = >> + (rx_max_lane_count > dp_tx->max_lane_count) ? >> + dp_tx->max_lane_count : rx_max_lane_count; >> + if (!is_lane_count_valid(dev, rx_max_lane_count)) >> + return -EINVAL; >> + >> + dp_tx->link_config.support_enhanced_framing_mode = >> + dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & >> + DPCD_ENHANCED_FRAME_SUPPORT_MASK; >> + dp_tx->link_config.support_downspread_control = >> + dp_tx->dpcd_rx_caps[DPCD_MAX_DOWNSPREAD] & >> + DPCD_MAX_DOWNSPREAD_MASK; >> + >> + return 0; >> +} >> + >> +static void enable_main_link(struct udevice *dev) >> +{ >> + /* reset the scrambler. */ >> + set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1); >> + >> + /* enable the main stream. */ >> + set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1); >> +} >> + >> +static void disable_main_link(struct udevice *dev) >> +{ >> + /* reset the scrambler. */ >> + set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1); >> + >> + /* Disable the main stream. */ >> + set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0); >> +} >> + >> +static void reset_dp_phy(struct udevice *dev, u32 reset) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + u32 val; >> + >> + set_reg(dev, REG_ENABLE, 0x0); >> + >> + val = get_reg(dev, REG_PHY_CONFIG); >> + >> + /* Apply reset. */ >> + set_reg(dev, REG_PHY_CONFIG, val | reset); >> + >> + /* Remove reset. */ >> + set_reg(dev, REG_PHY_CONFIG, val); >> + >> + /* Wait for the PHY to be ready. */ >> + wait_phy_ready(dev, >> PHY_STATUS_LANES_READY_MASK(dp_tx->max_lane_count)); >> + >> + set_reg(dev, REG_ENABLE, 0x1); >> +} >> + >> +/* >> + * enable or disable the enhanced framing symbol sequence for >> + * both the DisplayPort TX core and the RX device. >> + */ >> +static int set_enhanced_frame_mode(struct udevice *dev, u8 enable) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + int status; >> + u8 val; >> + >> + if (!is_connected(dev)) >> + return -ENODEV; >> + >> + if (dp_tx->link_config.support_enhanced_framing_mode) >> + dp_tx->link_config.enhanced_framing_mode = enable; >> + else >> + dp_tx->link_config.enhanced_framing_mode = false; >> + >> + /* Write enhanced frame mode enable to the DisplayPort TX core. */ >> + set_reg(dev, REG_ENHANCED_FRAME_EN, >> + dp_tx->link_config.enhanced_framing_mode); >> + >> + /* Write enhanced frame mode enable to the RX device. */ >> + status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val); >> + if (status) >> + return -EIO; >> + >> + if (dp_tx->link_config.enhanced_framing_mode) >> + val |= DPCD_ENHANCED_FRAME_EN_MASK; >> + else >> + val &= ~DPCD_ENHANCED_FRAME_EN_MASK; >> + >> + status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val); >> + if (status) >> + return -EIO; >> + >> + return 0; >> +} >> + >> +/* >> + * Set the number of lanes to be used by the main link for both >> + * the DisplayPort TX core and the RX device. >> + */ >> +static int set_lane_count(struct udevice *dev, u8 lane_count) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + int status; >> + u8 val; >> + >> + if (!is_connected(dev)) >> + return -ENODEV; >> + >> + printf(" set lane count to %u\n", lane_count); >> + >> + dp_tx->link_config.lane_count = lane_count; >> + >> + /* Write the new lane count to the DisplayPort TX core. */ >> + set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count); >> + >> + /* Write the new lane count to the RX device. */ >> + status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val); >> + if (status) >> + return -EIO; >> + val &= ~DPCD_LANE_COUNT_SET_MASK; >> + val |= dp_tx->link_config.lane_count; >> + >> + status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val); >> + if (status) >> + return -EIO; >> + >> + return 0; >> +} >> + >> +/* >> + * Set the clock frequency for the DisplayPort PHY corresponding >> + * to a desired data rate. >> + */ >> +static int set_clk_speed(struct udevice *dev, u32 speed) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + int status; >> + u32 val; >> + >> + /* Disable the DisplayPort TX core first. */ >> + val = get_reg(dev, REG_ENABLE); >> + set_reg(dev, REG_ENABLE, 0x0); >> + >> + /* Change speed of the feedback clock. */ >> + set_reg(dev, REG_PHY_CLOCK_SELECT, speed); >> + >> + /* Re-enable the DisplayPort TX core if it was previously enabled. */ >> + if (val) >> + set_reg(dev, REG_ENABLE, 0x1); >> + >> + /* Wait until the PHY is ready. */ >> + status = wait_phy_ready(dev, >> PHY_STATUS_LANES_READY_MASK(dp_tx->max_lane_count)); >> + if (status) >> + return -EIO; >> + >> + return 0; >> +} >> + >> +/* >> + * Set the data rate to be used by the main link for both the >> + * DisplayPort TX core and the RX device. >> + */ >> +static int set_link_rate(struct udevice *dev, u8 link_rate) >> +{ >> + struct dp_tx *dp_tx = dev_get_priv(dev); >> + int status; >> + >> + /* Write a corresponding clock frequency to the DisplayPort TX core. >> */ >> + switch (link_rate) { >> + case LINK_BW_SET_162GBPS: >> + printf(" set link rate to 1.62 Gb/s\n"); >> + status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS); >> + break; >> + case LINK_BW_SET_270GBPS: >> + printf(" set link rate to 2.70 Gb/s\n"); >> + status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS); >> + break; >> + case LINK_BW_SET_540GBPS: >> + printf(" set link rate to 5.40 Gb/s\n"); >> + status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS); >> + break; >> + default: >> + return -EINVAL; >> + } >> + if (status) >> + return -EIO; >> + >> + dp_tx->link_config.link_rate = link_rate; >> + >> + /* Write new link rate to the DisplayPort TX core. */ >> + set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate); >> + >> + /* Write new link rate to the RX device. */ >> + status = aux_write(dev, DPCD_LINK_BW_SET, 1, >> + &dp_tx->link_config.link_rate); >> + if (status) >> + return -EIO; > > Can you not return the error you got from aux_write()? > I'll return the aux_write error code in v2. > [..] > > Regards, > Simon Best regards, Mario _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot