Dear Lasse Skov,

please keep the list on Cc:

In message <[email protected]> you 
wrote:
> 
> I had now fixed some settings on the DDR2 timing, found something with the 
> ODT and other timing specific for the timing_cfg register.

Will you *please* keep your line length below some 70 charactes or so?
Thanks.

> And included some sync for the cache, but here im not quite sure on that this 
> is correct.
> 
> I had also let my board test the all the address range for my ram from 
> 0x0x20000000 (512MB)
> With the following code.
> 
> int testdram(void)
> {
>       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
>       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
>       uint *p;
>       printf("Testing DRAM from 0x%08x to 0x%08x\n",
>              CONFIG_SYS_MEMTEST_START,
>              CONFIG_SYS_MEMTEST_END);
> 
>       printf("DRAM test phase 1:\n");
>       for (p = pstart; p < pend; p++)
>               *p = (uint)p%8?0x5A5A5A5A:0xA5A5A5A5;
> 
>       for (p = pstart; p < pend; p++) {
>               if (*p !=  ((uint)p%8?0x5A5A5A5A:0xA5A5A5A5)) {
>                       printf("DRAM test fails at: %08x\n", (uint) p);
>                       return 1;
>               }
>       }
>       printf("DRAM test phase 2:\n");
>       for (p = pstart; p < pend; p++)
>               *p = (uint)p%8?0xA5A5A5A5:0x5A5A5A5A;
>       for (p = pstart; p < pend; p++) {
>               if (*p !=  ((uint)p%8?0xA5A5A5A5:0xA5A5A5A5A)) {
>                       printf("DRAM test fails at: %08x\n", (uint) p);
>                       return 1;
>               }
>       }
>       printf("DRAM test passed.\n");
>       return 0;
> }
> 
> Just some testcode i found and modified it a little bit. But the thing is 
> that this completes with succes.

This is a really braindead test. And like almost all memory tests it
will only exercise simple read and write accesses on the bus - it
cannot test burst mode accesses. Please see the FAQ:
http://www.denx.de/wiki/view/DULG/UBootCrashAfterRelocation

> I know that this is only running from flash and takes a lot of time to test 
> the 512Mb.
> 
> So because this is only running from Flash, I cannot be sure on that my SDRAM 
> configurations is correct?
> Or is this not a right conclusion?

Let's rephrase this: you can be pretty sure that your SDRAM
initialization is _not_ correct.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected]
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