On 07/09/2017 07:41 PM, Ran Wang wrote: > The default setting for USB High Speed Squelch Threshold results > in a threshold close to or lower than 100mV. This leads to Receiver > Compliance test failure for a 100mV threshold. > > The changes shift the threshold from ~100mV woards ~130mV resulting > in passing of USB High Speed Receiver Sensitivity Compliance test. > > Signed-off-by: Sriram Dash <[email protected]> > Signed-off-by: Rajesh Bhagat <[email protected]> > Signed-off-by: Suresh Gupta <[email protected]> > Signed-off-by: Ran Wang <[email protected]> > --- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 +++++ > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 > +++++++++++++++++++++ > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > 4 files changed, 28 insertions(+) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > index eebfcfe..63f4eec 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > @@ -23,6 +23,7 @@ config ARCH_LS1043A > select SYS_FSL_ERRATUM_A010315 > select SYS_FSL_ERRATUM_A010539 > select SYS_FSL_ERRATUM_A009008 > + select SYS_FSL_ERRATUM_A009798 > select SYS_FSL_HAS_DDR3 > select SYS_FSL_HAS_DDR4 > select ARCH_EARLY_INIT_R > @@ -44,6 +45,7 @@ config ARCH_LS1046A > select SYS_FSL_ERRATUM_A010165 > select SYS_FSL_ERRATUM_A010539 > select SYS_FSL_ERRATUM_A009008 > + select SYS_FSL_ERRATUM_A009798 > select SYS_FSL_HAS_DDR4 > select SYS_FSL_SRDS_2 > select ARCH_EARLY_INIT_R > @@ -80,6 +82,7 @@ config ARCH_LS2080A > select SYS_FSL_ERRATUM_A010165 > select SYS_FSL_ERRATUM_A009203 > select SYS_FSL_ERRATUM_A009008 > + select SYS_FSL_ERRATUM_A009798 > select ARCH_EARLY_INIT_R > select BOARD_EARLY_INIT_F > > @@ -226,6 +229,8 @@ config SYS_FSL_ERRATUM_A010539 > config SYS_FSL_ERRATUM_A009008 > bool "Workaround for USB PHY erratum A009008" > > +config SYS_FSL_ERRATUM_A009798 > + bool "Workaround for USB PHY erratum A009798" > > config MAX_CPUS > int "Maximum number of CPUs permitted for Layerscape" > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > index a91f85e..ad9127a 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > @@ -75,6 +75,25 @@ static void erratum_a009008(void) > #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ > } > > +static void erratum_a009798(void) > +{ > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 > +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) > + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; > + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
Put a blank line here. > + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE); > + val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); > + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE); > + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); > + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE); > +#elif defined(CONFIG_ARCH_LS2080A) > + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; Same here. Move it up together if you can. > + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); Put a blank line here. York _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
