On 07/09/2017 07:41 PM, Ran Wang wrote:
> The default setting for USB High Speed Squelch Threshold results
> in a threshold close to or lower than 100mV. This leads to Receive
> Compliance test failure for a 100mV threshold.
>
> The changes shift the threshold from ~100mV towards ~130mV resulting
> in passing of USB High Speed Receiver Sensitivity Compliance test.
>
> Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
> Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> Signed-off-by: Ran Wang <ran.wan...@nxp.com>
> ---
> arch/arm/cpu/armv7/ls102xa/Kconfig | 8 +++++++-
> arch/arm/cpu/armv7/ls102xa/soc.c | 9 +++++++++
> arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
> 3 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig
> b/arch/arm/cpu/armv7/ls102xa/Kconfig
> index 11e33d6..c605fc0 100644
> --- a/arch/arm/cpu/armv7/ls102xa/Kconfig
> +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
> @@ -6,6 +6,7 @@ config ARCH_LS1021A
> select SYS_FSL_ERRATUM_A009942
> select SYS_FSL_ERRATUM_A010315
> select SYS_FSL_ERRATUM_A009008
> + select SYS_FSL_ERRATUM_A009798
> select SYS_FSL_SRDS_1
> select SYS_HAS_SERDES
> select SYS_FSL_DDR_BE if SYS_FSL_DDR
> @@ -54,7 +55,12 @@ config SYS_FSL_ERRATUM_A010315
> config SYS_FSL_ERRATUM_A009008
> bool
> help
> - Workaround for USB erratum A009008
> + Workaround for USB PHY erratum A009008
> +
> +config SYS_FSL_ERRATUM_A009798
> + bool
> + help
> + Workaround for USB PHY erratum A009798
>
> config SYS_FSL_SRDS_1
> bool
> diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c
> b/arch/arm/cpu/armv7/ls102xa/soc.c
> index 986337d..ef44a6c 100644
> --- a/arch/arm/cpu/armv7/ls102xa/soc.c
> +++ b/arch/arm/cpu/armv7/ls102xa/soc.c
> @@ -70,6 +70,14 @@ static void erratum_a009008(void)
> #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
> }
>
> +static void erratum_a009798(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
> + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
> + u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
Put a blank line here.
York
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