Hi Tom,
On 2017/8/7 21:55, Tom Rini wrote:
On Thu, Jul 20, 2017 at 04:28:47PM +0800, wenyou.y...@microchip.com wrote:
Because before switching to a lower clock source, we must switch
the clock source first instead of last. So before configuring the
PMC_MCKR register, invoke at91_mck_init_down() first.
As said in datasheet, the the size of SPL must not exceed the maximum
size allowed(64Kbytes).
Signed-off-by: Wenyou Yang <wenyou.y...@microchip.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
The patch is based on
[PATCH 0/6] board: atmel: Add new board: SAMA5D27-SOM1-EK board
https://lists.denx.de/pipermail/u-boot/2017-July/298815.html
board/atmel/sama5d2_xplained/sama5d2_xplained.c | 10 ++++++++++
include/configs/sama5d2_xplained.h | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 48f45b35ce..8fd7eb8af1 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -285,6 +285,16 @@ void at91_pmc_init(void)
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
What patch adds the at91_mck_init_down function? Thanks!
It is in the patch,
https://lists.denx.de/pipermail/u-boot/2017-August/301111.html
Best Regards,
Wenyou Yang
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