From: Tien Fong Chee <tien.fong.c...@intel.com>
This function is required in both SPL and U-boot such as checking
boot device type, which is required for locating flash where U-boot
image, and FPGA design are stored.
Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
---
arch/arm/mach-socfpga/misc.c | 30 ++++++++++++++++++++++++++++++
arch/arm/mach-socfpga/spl.c | 29 -----------------------------
2 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 00eff90..e7d5ae8 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -12,6 +12,7 @@
#include <altera.h>
#include <miiphy.h>
#include <netdev.h>
+#include <spl.h>
#include <watchdog.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
@@ -26,6 +27,9 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
struct bsel bsel_str[] = {
{ "rsvd", "Reserved", },
{ "fpga", "FPGA (HPS2FPGA Bridge)", },
@@ -37,6 +41,32 @@ struct bsel bsel_str[] = {
{ "qspi", "QSPI Flash (3.0V)", },
};
+u32 spl_boot_device(void)
+{
+ const u32 bsel = readl(&sysmgr_regs->bootinfo);
+
+ switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+ case 0x1: /* FPGA (HPS2FPGA Bridge) */
+ return BOOT_DEVICE_RAM;
+ case 0x2: /* NAND Flash (1.8V) */
+ case 0x3: /* NAND Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+ return BOOT_DEVICE_NAND;
+ case 0x4: /* SD/MMC External Transceiver (1.8V) */
+ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+ socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+ return BOOT_DEVICE_MMC1;
+ case 0x6: /* QSPI Flash (1.8V) */
+ case 0x7: /* QSPI Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+ return BOOT_DEVICE_SPI;
+ default:
+ printf("Invalid boot device (bsel=%08x)!\n", bsel);
+ hang();
+ }
+}
+
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 71bae82..175d546 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -37,35 +37,6 @@ static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
#endif
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
-u32 spl_boot_device(void)
-{
- const u32 bsel = readl(&sysmgr_regs->bootinfo);
-
- switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
- case 0x1: /* FPGA (HPS2FPGA Bridge) */
- return BOOT_DEVICE_RAM;
- case 0x2: /* NAND Flash (1.8V) */
- case 0x3: /* NAND Flash (3.0V) */
- socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
- return BOOT_DEVICE_NAND;
- case 0x4: /* SD/MMC External Transceiver (1.8V) */
- case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
- socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
- socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
- return BOOT_DEVICE_MMC1;
- case 0x6: /* QSPI Flash (1.8V) */
- case 0x7: /* QSPI Flash (3.0V) */
- socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
- return BOOT_DEVICE_SPI;
- default:
- printf("Invalid boot device (bsel=%08x)!\n", bsel);
- hang();
- }
-}
-
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(const u32 boot_device)
{
--
2.2.0
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