On 28/08/2017 17:46, Anatolij Gustschin wrote: > There is no need to clear the control register 100 times in a > loop, a single zero write clears the register. I didn't find any > justification why clearing this register in a loop is needed > (no info in i.MX6 errata or GPT timer linux driver, linux driver > uses single write to clear this control register). > > Signed-off-by: Anatolij Gustschin <ag...@denx.de> > --- > arch/arm/mach-imx/timer.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c > index 9b01114..69dbf3c 100644 > --- a/arch/arm/mach-imx/timer.c > +++ b/arch/arm/mach-imx/timer.c > @@ -74,8 +74,7 @@ int timer_init(void) > __raw_writel(GPTCR_SWR, &cur_gpt->control); > > /* We have no udelay by now */ > - for (i = 0; i < 100; i++) > - __raw_writel(0, &cur_gpt->control); > + __raw_writel(0, &cur_gpt->control); > > i = __raw_readl(&cur_gpt->control); > i &= ~GPTCR_CLKSOURCE_MASK; >
Applied to u-boot-imx, -master, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
