[U-Boot] [PATCH] armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC

[Sriram Dash]

IFC code is put under CONFIG_FSL_IFC

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c        |  2 ++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 639e9d2..a538d76 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -192,7 +192,9 @@ void bypass_smmu(void)
 void fsl_lsch3_early_init_f(void)
 {
        erratum_rcw_src();
+#ifdef CONFIG_FSL_IFC
        init_early_memctl_regs();       /* tighten IFC timing */
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
        erratum_a009203();
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index c4e5ecc..f231688 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -102,6 +102,7 @@ static struct mm_region early_map[] = {
        { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
          CONFIG_SYS_FSL_QSPI_SIZE1,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
        /* For IFC Region #1, only the first 4MB is cache-enabled */
        { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
          CONFIG_SYS_FSL_IFC_SIZE1_1,
@@ -116,6 +117,7 @@ static struct mm_region early_map[] = {
          CONFIG_SYS_FSL_IFC_SIZE1,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -125,11 +127,13 @@ static struct mm_region early_map[] = {
 #endif
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
+#ifdef CONFIG_FSL_IFC
        /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
          CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -159,10 +163,12 @@ static struct mm_region early_map[] = {
          CONFIG_SYS_FSL_QSPI_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#ifdef CONFIG_FSL_IFC
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -206,10 +212,12 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#ifdef CONFIG_FSL_IFC
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
          CONFIG_SYS_FSL_IFC_SIZE2,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -304,10 +312,12 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#ifdef CONFIG_FSL_IFC
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
        },
+#endif
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-- 
1.9.1

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