If 64-bit capability is supported, commandlistbase and fis base
should be split as lower32 and upper32. upper32 should be
written to PORT_(LST/FIS)_ADDR_HI.
Signed-off-by: Suneel Garapati <suneelgli...@gmail.com>
---
Changes v1:
- add macro definitions for LOWER32, UPPER32
drivers/ata/ahci.c | 14 ++++++++++++--
include/ahci.h | 1 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5e4df19..178d9a7 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -27,6 +27,9 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
+#define LOWER32(val) (u32)((u64)(val) & 0xFFFFFFFF)
+#define UPPER32(val) (u32)(((u64)(val) & 0xFFFFFFFF00000000ULL) >> 32)
+
static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
#ifndef CONFIG_DM_SCSI
@@ -607,10 +610,17 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv,
u8 port)
pp->cmd_tbl_sg =
(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
- writel_with_flush((unsigned long)pp->cmd_slot,
+ if (uc_priv->cap & HOST_CAP_64)
+ writel_with_flush(cpu_to_le32(UPPER32(pp->cmd_slot)),
+ port_mmio + PORT_LST_ADDR_HI);
+ writel_with_flush(cpu_to_le32(LOWER32(pp->cmd_slot)),
port_mmio + PORT_LST_ADDR);
- writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+ if (uc_priv->cap & HOST_CAP_64)
+ writel_with_flush(cpu_to_le32(UPPER32(pp->rx_fis)),
+ port_mmio + PORT_FIS_ADDR_HI);
+ writel_with_flush(cpu_to_le32(LOWER32(pp->rx_fis)),
+ port_mmio + PORT_FIS_ADDR);
#ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);
diff --git a/include/ahci.h b/include/ahci.h
index 33171b7..80e7f13 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -40,6 +40,7 @@
#define HOST_RESET (1 << 0) /* reset controller; self-clear */
#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
+#define HOST_CAP_64 (1 << 31) /* 64bit addressing capability */
/* Registers for each SATA port */
#define PORT_LST_ADDR 0x00 /* command list DMA addr */
--
2.7.4
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