It was recently discovered that the USB PHY control register offset on
the A83T is 0x410 like on the A33, not 0x404. Fix it.
Fixes: 0c935acb9e5d ("sunxi: usb_phy: Add support for A83T USB PHYs")
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/mach-sunxi/usb_phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index 9bf0b5633d4a..3fbef0050e3f 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -19,7 +19,7 @@
#include <errno.h>
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T
#define SUNXI_USB_CSR 0x410
#else
#define SUNXI_USB_CSR 0x404
--
2.14.1
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