> On 27 Sep 2017, at 10:38, Kever Yang <kever.y...@rock-chips.com> wrote: > > Add driver for rk322x to support sdram initialize in SPL. > > Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> As previously discussed, I'll merge this in its current form (i.e. duplicating code and data structures) with a commitment (AFAIK there is work ongoing towards this goal at Rockchip, but it will take a while to complete) to unify our DRAM drivers in one of the upcoming merge windows. > --- > > Changes in v4: > - rebase on u-boot-rockchip master with patchset "move rockchip sdram > driver to driver/ram” Thanks for doing this. This saves me a lot of work. Regards, Philipp. > Changes in v3: > - move rk332x sdram driver to driver/ram > - do the ram init in TPL instad of SPL > > arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 581 +++++++++++++++ > drivers/ram/rockchip/Makefile | 1 + > drivers/ram/rockchip/sdram_rk322x.c | 855 ++++++++++++++++++++++ > 3 files changed, 1437 insertions(+) > create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk322x.h > create mode 100644 drivers/ram/rockchip/sdram_rk322x.c > > diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h > b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h > new file mode 100644 > index 0000000..b40da40 > --- /dev/null > +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h > @@ -0,0 +1,581 @@ > +/* > + * (C) Copyright 2017 Rockchip Electronics Co., Ltd > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +#ifndef _ASM_ARCH_SDRAM_RK322X_H > +#define _ASM_ARCH_SDRAM_RK322X_H > + > +#include <common.h> > + > +enum { > + DDR3 = 3, > + LPDDR2 = 5, > + LPDDR3 = 6, > + UNUSED = 0xFF, > +}; > + > +struct rk322x_sdram_channel { > + /* > + * bit width in address, eg: > + * 8 banks using 3 bit to address, > + * 2 cs using 1 bit to address. > + */ > + u8 rank; > + u8 col; > + u8 bk; > + u8 bw; > + u8 dbw; > + u8 row_3_4; > + u8 cs0_row; > + u8 cs1_row; > +#if CONFIG_IS_ENABLED(OF_PLATDATA) > + /* > + * For of-platdata, which would otherwise convert this into two > + * byte-swapped integers. With a size of 9 bytes, this struct will > + * appear in of-platdata as a byte array. > + * > + * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) > + */ > + u8 dummy; > +#endif > +}; > + > +struct rk322x_ddr_pctl { > + u32 scfg; > + u32 sctl; > + u32 stat; > + u32 intrstat; > + u32 reserved0[(0x40 - 0x10) / 4]; > + u32 mcmd; > + u32 powctl; > + u32 powstat; > + u32 cmdtstat; > + u32 cmdtstaten; > + u32 reserved1[(0x60 - 0x54) / 4]; > + u32 mrrcfg0; > + u32 mrrstat0; > + u32 mrrstat1; > + u32 reserved2[(0x7c - 0x6c) / 4]; > + > + u32 mcfg1; > + u32 mcfg; > + u32 ppcfg; > + u32 mstat; > + u32 lpddr2zqcfg; > + u32 reserved3; > + > + u32 dtupdes; > + u32 dtuna; > + u32 dtune; > + u32 dtuprd0; > + u32 dtuprd1; > + u32 dtuprd2; > + u32 dtuprd3; > + u32 dtuawdt; > + u32 reserved4[(0xc0 - 0xb4) / 4]; > + > + u32 togcnt1u; > + u32 tinit; > + u32 trsth; > + u32 togcnt100n; > + u32 trefi; > + u32 tmrd; > + u32 trfc; > + u32 trp; > + u32 trtw; > + u32 tal; > + u32 tcl; > + u32 tcwl; > + u32 tras; > + u32 trc; > + u32 trcd; > + u32 trrd; > + u32 trtp; > + u32 twr; > + u32 twtr; > + u32 texsr; > + u32 txp; > + u32 txpdll; > + u32 tzqcs; > + u32 tzqcsi; > + u32 tdqs; > + u32 tcksre; > + u32 tcksrx; > + u32 tcke; > + u32 tmod; > + u32 trstl; > + u32 tzqcl; > + u32 tmrr; > + u32 tckesr; > + u32 tdpd; > + u32 tref_mem_ddr3; > + u32 reserved5[(0x180 - 0x14c) / 4]; > + u32 ecccfg; > + u32 ecctst; > + u32 eccclr; > + u32 ecclog; > + u32 reserved6[(0x200 - 0x190) / 4]; > + u32 dtuwactl; > + u32 dturactl; > + u32 dtucfg; > + u32 dtuectl; > + u32 dtuwd0; > + u32 dtuwd1; > + u32 dtuwd2; > + u32 dtuwd3; > + u32 dtuwdm; > + u32 dturd0; > + u32 dturd1; > + u32 dturd2; > + u32 dturd3; > + u32 dtulfsrwd; > + u32 dtulfsrrd; > + u32 dtueaf; > + /* dfi control registers */ > + u32 dfitctrldelay; > + u32 dfiodtcfg; > + u32 dfiodtcfg1; > + u32 dfiodtrankmap; > + /* dfi write data registers */ > + u32 dfitphywrdata; > + u32 dfitphywrlat; > + u32 reserved7[(0x260 - 0x258) / 4]; > + u32 dfitrddataen; > + u32 dfitphyrdlat; > + u32 reserved8[(0x270 - 0x268) / 4]; > + u32 dfitphyupdtype0; > + u32 dfitphyupdtype1; > + u32 dfitphyupdtype2; > + u32 dfitphyupdtype3; > + u32 dfitctrlupdmin; > + u32 dfitctrlupdmax; > + u32 dfitctrlupddly; > + u32 reserved9; > + u32 dfiupdcfg; > + u32 dfitrefmski; > + u32 dfitctrlupdi; > + u32 reserved10[(0x2ac - 0x29c) / 4]; > + u32 dfitrcfg0; > + u32 dfitrstat0; > + u32 dfitrwrlvlen; > + u32 dfitrrdlvlen; > + u32 dfitrrdlvlgateen; > + u32 dfiststat0; > + u32 dfistcfg0; > + u32 dfistcfg1; > + u32 reserved11; > + u32 dfitdramclken; > + u32 dfitdramclkdis; > + u32 dfistcfg2; > + u32 dfistparclr; > + u32 dfistparlog; > + u32 reserved12[(0x2f0 - 0x2e4) / 4]; > + > + u32 dfilpcfg0; > + u32 reserved13[(0x300 - 0x2f4) / 4]; > + u32 dfitrwrlvlresp0; > + u32 dfitrwrlvlresp1; > + u32 dfitrwrlvlresp2; > + u32 dfitrrdlvlresp0; > + u32 dfitrrdlvlresp1; > + u32 dfitrrdlvlresp2; > + u32 dfitrwrlvldelay0; > + u32 dfitrwrlvldelay1; > + u32 dfitrwrlvldelay2; > + u32 dfitrrdlvldelay0; > + u32 dfitrrdlvldelay1; > + u32 dfitrrdlvldelay2; > + u32 dfitrrdlvlgatedelay0; > + u32 dfitrrdlvlgatedelay1; > + u32 dfitrrdlvlgatedelay2; > + u32 dfitrcmd; > + u32 reserved14[(0x3f8 - 0x340) / 4]; > + u32 ipvr; > + u32 iptr; > +}; > +check_member(rk322x_ddr_pctl, iptr, 0x03fc); > + > +struct rk322x_ddr_phy { > + u32 ddrphy_reg[0x100]; > +}; > + > +struct rk322x_pctl_timing { > + u32 togcnt1u; > + u32 tinit; > + u32 trsth; > + u32 togcnt100n; > + u32 trefi; > + u32 tmrd; > + u32 trfc; > + u32 trp; > + u32 trtw; > + u32 tal; > + u32 tcl; > + u32 tcwl; > + u32 tras; > + u32 trc; > + u32 trcd; > + u32 trrd; > + u32 trtp; > + u32 twr; > + u32 twtr; > + u32 texsr; > + u32 txp; > + u32 txpdll; > + u32 tzqcs; > + u32 tzqcsi; > + u32 tdqs; > + u32 tcksre; > + u32 tcksrx; > + u32 tcke; > + u32 tmod; > + u32 trstl; > + u32 tzqcl; > + u32 tmrr; > + u32 tckesr; > + u32 tdpd; > + u32 trefi_mem_ddr3; > +}; > + > +struct rk322x_phy_timing { > + u32 mr[4]; > + u32 mr11; > + u32 bl; > + u32 cl_al; > +}; > + > +struct rk322x_msch_timings { > + u32 ddrtiming; > + u32 ddrmode; > + u32 readlatency; > + u32 activate; > + u32 devtodev; > +}; > + > +struct rk322x_service_sys { > + u32 id_coreid; > + u32 id_revisionid; > + u32 ddrconf; > + u32 ddrtiming; > + u32 ddrmode; > + u32 readlatency; > + u32 activate; > + u32 devtodev; > +}; > + > +struct rk322x_base_params { > + struct rk322x_msch_timings noc_timing; > + u32 ddrconfig; > + u32 ddr_freq; > + u32 dramtype; > + /* > + * unused for rk322x > + */ > + u32 stride; > + u32 odt; > +}; > + > +/* PCT_DFISTCFG0 */ > +#define DFI_INIT_START BIT(0) > +#define DFI_DATA_BYTE_DISABLE_EN BIT(2) > + > +/* PCT_DFISTCFG1 */ > +#define DFI_DRAM_CLK_SR_EN BIT(0) > +#define DFI_DRAM_CLK_DPD_EN BIT(1) > + > +/* PCT_DFISTCFG2 */ > +#define DFI_PARITY_INTR_EN BIT(0) > +#define DFI_PARITY_EN BIT(1) > + > +/* PCT_DFILPCFG0 */ > +#define TLP_RESP_TIME_SHIFT 16 > +#define LP_SR_EN BIT(8) > +#define LP_PD_EN BIT(0) > + > +/* PCT_DFITCTRLDELAY */ > +#define TCTRL_DELAY_TIME_SHIFT 0 > + > +/* PCT_DFITPHYWRDATA */ > +#define TPHY_WRDATA_TIME_SHIFT 0 > + > +/* PCT_DFITPHYRDLAT */ > +#define TPHY_RDLAT_TIME_SHIFT 0 > + > +/* PCT_DFITDRAMCLKDIS */ > +#define TDRAM_CLK_DIS_TIME_SHIFT 0 > + > +/* PCT_DFITDRAMCLKEN */ > +#define TDRAM_CLK_EN_TIME_SHIFT 0 > + > +/* PCTL_DFIODTCFG */ > +#define RANK0_ODT_WRITE_SEL BIT(3) > +#define RANK1_ODT_WRITE_SEL BIT(11) > + > +/* PCTL_DFIODTCFG1 */ > +#define ODT_LEN_BL8_W_SHIFT 16 > + > +/* PUBL_ACDLLCR */ > +#define ACDLLCR_DLLDIS BIT(31) > +#define ACDLLCR_DLLSRST BIT(30) > + > +/* PUBL_DXDLLCR */ > +#define DXDLLCR_DLLDIS BIT(31) > +#define DXDLLCR_DLLSRST BIT(30) > + > +/* PUBL_DLLGCR */ > +#define DLLGCR_SBIAS BIT(30) > + > +/* PUBL_DXGCR */ > +#define DQSRTT BIT(9) > +#define DQRTT BIT(10) > + > +/* PIR */ > +#define PIR_INIT BIT(0) > +#define PIR_DLLSRST BIT(1) > +#define PIR_DLLLOCK BIT(2) > +#define PIR_ZCAL BIT(3) > +#define PIR_ITMSRST BIT(4) > +#define PIR_DRAMRST BIT(5) > +#define PIR_DRAMINIT BIT(6) > +#define PIR_QSTRN BIT(7) > +#define PIR_RVTRN BIT(8) > +#define PIR_ICPC BIT(16) > +#define PIR_DLLBYP BIT(17) > +#define PIR_CTLDINIT BIT(18) > +#define PIR_CLRSR BIT(28) > +#define PIR_LOCKBYP BIT(29) > +#define PIR_ZCALBYP BIT(30) > +#define PIR_INITBYP BIT(31) > + > +/* PGCR */ > +#define PGCR_DFTLMT_SHIFT 3 > +#define PGCR_DFTCMP_SHIFT 2 > +#define PGCR_DQSCFG_SHIFT 1 > +#define PGCR_ITMDMD_SHIFT 0 > + > +/* PGSR */ > +#define PGSR_IDONE BIT(0) > +#define PGSR_DLDONE BIT(1) > +#define PGSR_ZCDONE BIT(2) > +#define PGSR_DIDONE BIT(3) > +#define PGSR_DTDONE BIT(4) > +#define PGSR_DTERR BIT(5) > +#define PGSR_DTIERR BIT(6) > +#define PGSR_DFTERR BIT(7) > +#define PGSR_RVERR BIT(8) > +#define PGSR_RVEIRR BIT(9) > + > +/* PTR0 */ > +#define PRT_ITMSRST_SHIFT 18 > +#define PRT_DLLLOCK_SHIFT 6 > +#define PRT_DLLSRST_SHIFT 0 > + > +/* PTR1 */ > +#define PRT_DINIT0_SHIFT 0 > +#define PRT_DINIT1_SHIFT 19 > + > +/* PTR2 */ > +#define PRT_DINIT2_SHIFT 0 > +#define PRT_DINIT3_SHIFT 17 > + > +/* DCR */ > +#define DDRMD_LPDDR 0 > +#define DDRMD_DDR 1 > +#define DDRMD_DDR2 2 > +#define DDRMD_DDR3 3 > +#define DDRMD_LPDDR2_LPDDR3 4 > +#define DDRMD_MASK 7 > +#define DDRMD_SHIFT 0 > +#define PDQ_MASK 7 > +#define PDQ_SHIFT 4 > + > +/* DXCCR */ > +#define DQSNRES_MASK 0xf > +#define DQSNRES_SHIFT 8 > +#define DQSRES_MASK 0xf > +#define DQSRES_SHIFT 4 > + > +/* DTPR */ > +#define TDQSCKMAX_SHIFT 27 > +#define TDQSCKMAX_MASK 7 > +#define TDQSCK_SHIFT 24 > +#define TDQSCK_MASK 7 > + > +/* DSGCR */ > +#define DQSGX_SHIFT 5 > +#define DQSGX_MASK 7 > +#define DQSGE_SHIFT 8 > +#define DQSGE_MASK 7 > + > +/* SCTL */ > +#define INIT_STATE 0 > +#define CFG_STATE 1 > +#define GO_STATE 2 > +#define SLEEP_STATE 3 > +#define WAKEUP_STATE 4 > + > +/* STAT */ > +#define LP_TRIG_SHIFT 4 > +#define LP_TRIG_MASK 7 > +#define PCTL_STAT_MASK 7 > +#define INIT_MEM 0 > +#define CONFIG 1 > +#define CONFIG_REQ 2 > +#define ACCESS 3 > +#define ACCESS_REQ 4 > +#define LOW_POWER 5 > +#define LOW_POWER_ENTRY_REQ 6 > +#define LOW_POWER_EXIT_REQ 7 > + > +/* ZQCR*/ > +#define PD_OUTPUT_SHIFT 0 > +#define PU_OUTPUT_SHIFT 5 > +#define PD_ONDIE_SHIFT 10 > +#define PU_ONDIE_SHIFT 15 > +#define ZDEN_SHIFT 28 > + > +/* DDLGCR */ > +#define SBIAS_BYPASS BIT(23) > + > +/* MCFG */ > +#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 > +#define PD_IDLE_SHIFT 8 > +#define MDDR_EN (2 << 22) > +#define LPDDR2_EN (3 << 22) > +#define LPDDR3_EN (1 << 22) > +#define DDR2_EN (0 << 5) > +#define DDR3_EN (1 << 5) > +#define LPDDR2_S2 (0 << 6) > +#define LPDDR2_S4 (1 << 6) > +#define MDDR_LPDDR2_BL_2 (0 << 20) > +#define MDDR_LPDDR2_BL_4 (1 << 20) > +#define MDDR_LPDDR2_BL_8 (2 << 20) > +#define MDDR_LPDDR2_BL_16 (3 << 20) > +#define DDR2_DDR3_BL_4 0 > +#define DDR2_DDR3_BL_8 1 > +#define TFAW_SHIFT 18 > +#define PD_EXIT_SLOW (0 << 17) > +#define PD_EXIT_FAST (1 << 17) > +#define PD_TYPE_SHIFT 16 > +#define BURSTLENGTH_SHIFT 20 > + > +/* POWCTL */ > +#define POWER_UP_START BIT(0) > + > +/* POWSTAT */ > +#define POWER_UP_DONE BIT(0) > + > +/* MCMD */ > +enum { > + DESELECT_CMD = 0, > + PREA_CMD, > + REF_CMD, > + MRS_CMD, > + ZQCS_CMD, > + ZQCL_CMD, > + RSTL_CMD, > + MRR_CMD = 8, > + DPDE_CMD, > +}; > + > +#define BANK_ADDR_MASK 7 > +#define BANK_ADDR_SHIFT 17 > +#define CMD_ADDR_MASK 0x1fff > +#define CMD_ADDR_SHIFT 4 > + > +#define LPDDR23_MA_SHIFT 4 > +#define LPDDR23_MA_MASK 0xff > +#define LPDDR23_OP_SHIFT 12 > +#define LPDDR23_OP_MASK 0xff > + > +#define START_CMD (1u << 31) > + > +/* DDRPHY REG */ > +enum { > + /* DDRPHY_REG0 */ > + SOFT_RESET_MASK = 3, > + SOFT_DERESET_ANALOG = 1 << 2, > + SOFT_DERESET_DIGITAL = 1 << 3, > + SOFT_RESET_SHIFT = 2, > + > + /* DDRPHY REG1 */ > + PHY_DDR3 = 0, > + PHY_DDR2 = 1, > + PHY_LPDDR3 = 2, > + PHY_LPDDR2 = 3, > + > + PHT_BL_8 = 1 << 2, > + PHY_BL_4 = 0 << 2, > + > + /* DDRPHY_REG2 */ > + MEMORY_SELECT_DDR3 = 0 << 0, > + MEMORY_SELECT_LPDDR3 = 2 << 0, > + MEMORY_SELECT_LPDDR2 = 3 << 0, > + DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4, > + DQS_SQU_CAL_SEL_CS1 = 1 << 4, > + DQS_SQU_CAL_SEL_CS0 = 2 << 4, > + DQS_SQU_CAL_NORMAL_MODE = 0 << 1, > + DQS_SQU_CAL_BYPASS_MODE = 1 << 1, > + DQS_SQU_CAL_START = 1 << 0, > + DQS_SQU_NO_CAL = 0 << 0, > +}; > + > +/* CK pull up/down driver strength control */ > +enum { > + PHY_RON_RTT_DISABLE = 0, > + PHY_RON_RTT_451OHM = 1, > + PHY_RON_RTT_225OHM, > + PHY_RON_RTT_150OHM, > + PHY_RON_RTT_112OHM, > + PHY_RON_RTT_90OHM, > + PHY_RON_RTT_75OHM, > + PHY_RON_RTT_64OHM = 7, > + > + PHY_RON_RTT_56OHM = 16, > + PHY_RON_RTT_50OHM, > + PHY_RON_RTT_45OHM, > + PHY_RON_RTT_41OHM, > + PHY_RON_RTT_37OHM, > + PHY_RON_RTT_34OHM, > + PHY_RON_RTT_33OHM, > + PHY_RON_RTT_30OHM = 23, > + > + PHY_RON_RTT_28OHM = 24, > + PHY_RON_RTT_26OHM, > + PHY_RON_RTT_25OHM, > + PHY_RON_RTT_23OHM, > + PHY_RON_RTT_22OHM, > + PHY_RON_RTT_21OHM, > + PHY_RON_RTT_20OHM, > + PHY_RON_RTT_19OHM = 31, > +}; > + > +/* DQS squelch DLL delay */ > +enum { > + DQS_DLL_NO_DELAY = 0, > + DQS_DLL_22P5_DELAY, > + DQS_DLL_45_DELAY, > + DQS_DLL_67P5_DELAY, > + DQS_DLL_90_DELAY, > + DQS_DLL_112P5_DELAY, > + DQS_DLL_135_DELAY, > + DQS_DLL_157P5_DELAY, > +}; > + > +/* GRF_SOC_CON0 */ > +#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0)) > +#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0)) > +#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << > 7)) > +#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << > 7)) > + > +#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8)) > +#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8)) > + > +#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6)) > +#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << > 6)) > + > +#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n)) > +#define DDR3_DLL_RESET (1 << 8) > + > +#endif /* _ASM_ARCH_SDRAM_RK322X_H */ > diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile > index 6c78eff..45b5fe7 100644 > --- a/drivers/ram/rockchip/Makefile > +++ b/drivers/ram/rockchip/Makefile > @@ -6,6 +6,7 @@ > > obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o > obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o > +obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o > obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o > obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o > obj-$(CONFIG_ROCKCHIP_RK3399) = sdram_rk3399.o > diff --git a/drivers/ram/rockchip/sdram_rk322x.c > b/drivers/ram/rockchip/sdram_rk322x.c > new file mode 100644 > index 0000000..cc3138b > --- /dev/null > +++ b/drivers/ram/rockchip/sdram_rk322x.c > @@ -0,0 +1,855 @@ > +/* > + * (C) Copyright 2017 Rockchip Electronics Co., Ltd > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > +#include <common.h> > +#include <clk.h> > +#include <dm.h> > +#include <dt-structs.h> > +#include <errno.h> > +#include <ram.h> > +#include <regmap.h> > +#include <syscon.h> > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/cru_rk322x.h> > +#include <asm/arch/grf_rk322x.h> > +#include <asm/arch/hardware.h> > +#include <asm/arch/sdram_rk322x.h> > +#include <asm/arch/timer.h> > +#include <asm/arch/uart.h> > +#include <asm/arch/sdram_common.h> > +#include <asm/types.h> > +#include <linux/err.h> > + > +DECLARE_GLOBAL_DATA_PTR; > +struct chan_info { > + struct rk322x_ddr_pctl *pctl; > + struct rk322x_ddr_phy *phy; > + struct rk322x_service_sys *msch; > +}; > + > +struct dram_info { > + struct chan_info chan[1]; > + struct ram_info info; > + struct clk ddr_clk; > + struct rk322x_cru *cru; > + struct rk322x_grf *grf; > +}; > + > +struct rk322x_sdram_params { > +#if CONFIG_IS_ENABLED(OF_PLATDATA) > + struct dtd_rockchip_rk3228_dmc of_plat; > +#endif > + struct rk322x_sdram_channel ch[1]; > + struct rk322x_pctl_timing pctl_timing; > + struct rk322x_phy_timing phy_timing; > + struct rk322x_base_params base; > + int num_channels; > + struct regmap *map; > +}; > + > +#ifdef CONFIG_TPL_BUILD > +/* > + * [7:6] bank(n:n bit bank) > + * [5:4] row(13+n) > + * [3] cs(0:1 cs, 1:2 cs) > + * [2:1] bank(n:n bit bank) > + * [0] col(10+n) > + */ > +const char ddr_cfg_2_rbc[] = { > + ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 1), > + ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 1), > + ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 1), > + ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 1), > + ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 2), > + ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 2), > + ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 2), > + ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 0), > + ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 0), > + ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 0), > + ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 0), > + ((0 << 6) | (2 << 4) | (0 << 3) | (0 << 2) | 1), > + ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 2), > + ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 1), > + ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 1), > + ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 0), > +}; > + > +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) > +{ > + int i; > + > + for (i = 0; i < n / sizeof(u32); i++) { > + writel(*src, dest); > + src++; > + dest++; > + } > +} > + > +void phy_pctrl_reset(struct rk322x_cru *cru, > + struct rk322x_ddr_phy *ddr_phy) > +{ > + rk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | > + 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | > + 1 << DDRPHY_SRST_SHIFT, > + 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | > + 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); > + > + rockchip_udelay(10); > + > + rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | > + 1 << DDRPHY_SRST_SHIFT); > + rockchip_udelay(10); > + > + rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | > + 1 << DDRCTRL_SRST_SHIFT); > + rockchip_udelay(10); > + > + clrbits_le32(&ddr_phy->ddrphy_reg[0], > + SOFT_RESET_MASK << SOFT_RESET_SHIFT); > + rockchip_udelay(10); > + setbits_le32(&ddr_phy->ddrphy_reg[0], > + SOFT_DERESET_ANALOG); > + rockchip_udelay(5); > + setbits_le32(&ddr_phy->ddrphy_reg[0], > + SOFT_DERESET_DIGITAL); > + > + rockchip_udelay(1); > +} > + > +void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) > +{ > + u32 tmp; > + > + setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10); > + setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10); > + setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10); > + setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10); > + setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10); > + > + clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8); > + clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8); > + clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8); > + clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8); > + clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8); > + > + if (freq <= 400) > + setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); > + else > + clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); > + > + if (freq <= 680) > + tmp = 3; > + else > + tmp = 2; > + > + writel(tmp, &ddr_phy->ddrphy_reg[0x28]); > + writel(tmp, &ddr_phy->ddrphy_reg[0x38]); > + writel(tmp, &ddr_phy->ddrphy_reg[0x48]); > + writel(tmp, &ddr_phy->ddrphy_reg[0x58]); > +} > + > +static void send_command(struct rk322x_ddr_pctl *pctl, > + u32 rank, u32 cmd, u32 arg) > +{ > + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); > + rockchip_udelay(1); > + while (readl(&pctl->mcmd) & START_CMD) > + ; > +} > + > +static void memory_init(struct chan_info *chan, > + struct rk322x_sdram_params *sdram_params) > +{ > + struct rk322x_ddr_pctl *pctl = chan->pctl; > + u32 dramtype = sdram_params->base.dramtype; > + > + if (dramtype == DDR3) { > + send_command(pctl, 3, DESELECT_CMD, 0); > + rockchip_udelay(1); > + send_command(pctl, 3, PREA_CMD, 0); > + send_command(pctl, 3, MRS_CMD, > + (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | > + (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << > + CMD_ADDR_SHIFT); > + > + send_command(pctl, 3, MRS_CMD, > + (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | > + (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << > + CMD_ADDR_SHIFT); > + > + send_command(pctl, 3, MRS_CMD, > + (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | > + (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << > + CMD_ADDR_SHIFT); > + > + send_command(pctl, 3, MRS_CMD, > + (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | > + ((sdram_params->phy_timing.mr[0] | > + DDR3_DLL_RESET) & > + CMD_ADDR_MASK) << CMD_ADDR_SHIFT); > + > + send_command(pctl, 3, ZQCL_CMD, 0); > + } else { > + send_command(pctl, 3, MRS_CMD, > + (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | > + (0 & LPDDR23_OP_MASK) << > + LPDDR23_OP_SHIFT); > + rockchip_udelay(10); > + send_command(pctl, 3, MRS_CMD, > + (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | > + (0xff & LPDDR23_OP_MASK) << > + LPDDR23_OP_SHIFT); > + rockchip_udelay(1); > + send_command(pctl, 3, MRS_CMD, > + (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | > + (0xff & LPDDR23_OP_MASK) << > + LPDDR23_OP_SHIFT); > + rockchip_udelay(1); > + send_command(pctl, 3, MRS_CMD, > + (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | > + (sdram_params->phy_timing.mr[1] & > + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); > + send_command(pctl, 3, MRS_CMD, > + (2 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | > + (sdram_params->phy_timing.mr[2] & > + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); > + send_command(pctl, 3, MRS_CMD, > + (3 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | > + (sdram_params->phy_timing.mr[3] & > + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); > + if (dramtype == LPDDR3) > + send_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) << > + LPDDR23_MA_SHIFT | > + (sdram_params->phy_timing.mr11 & > + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); > + } > +} > + > +static u32 data_training(struct chan_info *chan) > +{ > + struct rk322x_ddr_phy *ddr_phy = chan->phy; > + struct rk322x_ddr_pctl *pctl = chan->pctl; > + u32 value; > + u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf; > + u32 ret; > + > + /* disable auto refresh */ > + value = readl(&pctl->trefi) | (1 << 31); > + writel(1 << 31, &pctl->trefi); > + > + clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30, > + DQS_SQU_CAL_SEL_CS0); > + setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); > + > + rockchip_udelay(30); > + ret = readl(&ddr_phy->ddrphy_reg[0xff]); > + > + clrbits_le32(&ddr_phy->ddrphy_reg[2], > + DQS_SQU_CAL_START); > + > + /* > + * since data training will take about 20us, so send some auto > + * refresh(about 7.8us) to complement the lost time > + */ > + send_command(pctl, 3, PREA_CMD, 0); > + send_command(pctl, 3, REF_CMD, 0); > + > + writel(value, &pctl->trefi); > + > + if (ret & 0x10) { > + ret = -1; > + } else { > + ret = (ret & 0xf) ^ bw; > + ret = (ret == 0) ? 0 : -1; > + } > + return ret; > +} > + > +static void move_to_config_state(struct rk322x_ddr_pctl *pctl) > +{ > + unsigned int state; > + > + while (1) { > + state = readl(&pctl->stat) & PCTL_STAT_MASK; > + switch (state) { > + case LOW_POWER: > + writel(WAKEUP_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) > + != ACCESS) > + ; > + /* > + * If at low power state, need wakeup first, and then > + * enter the config, so fallthrough > + */ > + case ACCESS: > + /* fallthrough */ > + case INIT_MEM: > + writel(CFG_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) > + ; > + break; > + case CONFIG: > + return; > + default: > + break; > + } > + } > +} > + > +static void move_to_access_state(struct rk322x_ddr_pctl *pctl) > +{ > + unsigned int state; > + > + while (1) { > + state = readl(&pctl->stat) & PCTL_STAT_MASK; > + switch (state) { > + case LOW_POWER: > + writel(WAKEUP_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) > + ; > + break; > + case INIT_MEM: > + writel(CFG_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) > + ; > + /* fallthrough */ > + case CONFIG: > + writel(GO_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) > + ; > + break; > + case ACCESS: > + return; > + default: > + break; > + } > + } > +} > + > +static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl) > +{ > + unsigned int state; > + > + while (1) { > + state = readl(&pctl->stat) & PCTL_STAT_MASK; > + switch (state) { > + case INIT_MEM: > + writel(CFG_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) > + ; > + /* fallthrough */ > + case CONFIG: > + writel(GO_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) > + ; > + break; > + case ACCESS: > + writel(SLEEP_STATE, &pctl->sctl); > + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != > + LOW_POWER) > + ; > + break; > + case LOW_POWER: > + return; > + default: > + break; > + } > + } > +} > + > +/* pctl should in low power mode when call this function */ > +static void phy_softreset(struct dram_info *dram) > +{ > + struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; > + struct rk322x_grf *grf = dram->grf; > + > + writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); > + clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); > + rockchip_udelay(1); > + setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); > + rockchip_udelay(5); > + setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); > + writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); > +} > + > +/* bw: 2: 32bit, 1:16bit */ > +static void set_bw(struct dram_info *dram, u32 bw) > +{ > + struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; > + struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; > + struct rk322x_grf *grf = dram->grf; > + > + if (bw == 1) { > + setbits_le32(&pctl->ppcfg, 1); > + clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4); > + writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]); > + clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); > + clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); > + } else { > + clrbits_le32(&pctl->ppcfg, 1); > + setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4); > + writel(GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN, > + &grf->soc_con[0]); > + setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); > + setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); > + } > +} > + > +static void pctl_cfg(struct rk322x_ddr_pctl *pctl, > + struct rk322x_sdram_params *sdram_params, > + struct rk322x_grf *grf) > +{ > + u32 burst_len; > + u32 bw; > + u32 dramtype = sdram_params->base.dramtype; > + > + if (sdram_params->ch[0].bw == 2) > + bw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN; > + else > + bw = GRF_MSCH_NOC_16BIT_EN; > + > + writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); > + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); > + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); > + writel(0x51010, &pctl->dfilpcfg0); > + > + writel(1, &pctl->dfitphyupdtype0); > + writel(0x0d, &pctl->dfitphyrdlat); > + writel(0, &pctl->dfitphywrdata); > + > + writel(0, &pctl->dfiupdcfg); > + copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, > + sizeof(struct rk322x_pctl_timing)); > + if (dramtype == DDR3) { > + writel((1 << 3) | (1 << 11), > + &pctl->dfiodtcfg); > + writel(7 << 16, &pctl->dfiodtcfg1); > + writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen); > + writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat); > + writel(500, &pctl->trsth); > + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | > + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | > + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, > + &pctl->mcfg); > + writel(bw | GRF_DDR3_EN, &grf->soc_con[0]); > + } else { > + if (sdram_params->phy_timing.bl & PHT_BL_8) > + burst_len = MDDR_LPDDR2_BL_8; > + else > + burst_len = MDDR_LPDDR2_BL_4; > + > + writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen); > + writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat); > + writel(0, &pctl->trsth); > + if (dramtype == LPDDR2) { > + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | > + LPDDR2_S4 | LPDDR2_EN | burst_len | > + (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | > + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, > + &pctl->mcfg); > + writel(0, &pctl->dfiodtcfg); > + writel(0, &pctl->dfiodtcfg1); > + } else { > + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | > + LPDDR2_S4 | LPDDR3_EN | burst_len | > + (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | > + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, > + &pctl->mcfg); > + writel((1 << 3) | (1 << 2), &pctl->dfiodtcfg); > + writel((7 << 16) | 4, &pctl->dfiodtcfg1); > + } > + writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]); > + } > + setbits_le32(&pctl->scfg, 1); > +} > + > +static void phy_cfg(struct chan_info *chan, > + struct rk322x_sdram_params *sdram_params) > +{ > + struct rk322x_ddr_phy *ddr_phy = chan->phy; > + struct rk322x_service_sys *axi_bus = chan->msch; > + struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing; > + struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing; > + struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing; > + u32 cmd_drv, clk_drv, dqs_drv, dqs_odt; > + > + writel(noc_timing->ddrtiming, &axi_bus->ddrtiming); > + writel(noc_timing->ddrmode, &axi_bus->ddrmode); > + writel(noc_timing->readlatency, &axi_bus->readlatency); > + writel(noc_timing->activate, &axi_bus->activate); > + writel(noc_timing->devtodev, &axi_bus->devtodev); > + > + switch (sdram_params->base.dramtype) { > + case DDR3: > + writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); > + break; > + case LPDDR2: > + writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); > + break; > + default: > + writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); > + break; > + } > + > + writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]); > + writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]); > + > + cmd_drv = PHY_RON_RTT_34OHM; > + clk_drv = PHY_RON_RTT_45OHM; > + dqs_drv = PHY_RON_RTT_34OHM; > + if (sdram_params->base.dramtype == LPDDR2) > + dqs_odt = PHY_RON_RTT_DISABLE; > + else > + dqs_odt = PHY_RON_RTT_225OHM; > + > + writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]); > + clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3); > + writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]); > + writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]); > + > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]); > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]); > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]); > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]); > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]); > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]); > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]); > + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]); > + > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]); > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]); > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]); > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]); > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]); > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]); > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]); > + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]); > +} > + > +void dram_cfg_rbc(struct chan_info *chan, > + struct rk322x_sdram_params *sdram_params) > +{ > + char noc_config; > + int i = 0; > + struct rk322x_sdram_channel *config = &sdram_params->ch[0]; > + struct rk322x_service_sys *axi_bus = chan->msch; > + > + move_to_config_state(chan->pctl); > + > + if ((config->rank == 2) && (config->cs1_row == config->cs0_row)) { > + if ((config->col + config->bw) == 12) { > + i = 14; > + goto finish; > + } else if ((config->col + config->bw) == 11) { > + i = 15; > + goto finish; > + } > + } > + noc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) | > + (config->col + config->bw - 11); > + for (i = 0; i < 11; i++) { > + if (noc_config == ddr_cfg_2_rbc[i]) > + break; > + } > + > + if (i < 11) > + goto finish; > + > + noc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) | > + (config->col + config->bw - 11); > + > + for (i = 11; i < 14; i++) { > + if (noc_config == ddr_cfg_2_rbc[i]) > + break; > + } > + if (i < 14) > + goto finish; > + else > + i = 0; > + > +finish: > + writel(i, &axi_bus->ddrconf); > + move_to_access_state(chan->pctl); > +} > + > +static void dram_all_config(const struct dram_info *dram, > + struct rk322x_sdram_params *sdram_params) > +{ > + struct rk322x_sdram_channel *info = &sdram_params->ch[0]; > + u32 sys_reg = 0; > + > + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; > + sys_reg |= (1 - 1) << SYS_REG_NUM_CH_SHIFT; > + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(0); > + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(0); > + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(0); > + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(0); > + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(0); > + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0); > + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(0); > + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(0); > + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0); > + > + writel(sys_reg, &dram->grf->os_reg[2]); > +} > + > +#define TEST_PATTEN 0x5aa5f00f > + > +static int dram_cap_detect(struct dram_info *dram, > + struct rk322x_sdram_params *sdram_params) > +{ > + u32 bw, row, col, addr; > + u32 ret = 0; > + struct rk322x_service_sys *axi_bus = dram->chan[0].msch; > + > + if (sdram_params->base.dramtype == DDR3) > + sdram_params->ch[0].dbw = 1; > + else > + sdram_params->ch[0].dbw = 2; > + > + move_to_config_state(dram->chan[0].pctl); > + /* bw detect */ > + set_bw(dram, 2); > + if (data_training(&dram->chan[0]) == 0) { > + bw = 2; > + } else { > + bw = 1; > + set_bw(dram, 1); > + move_to_lowpower_state(dram->chan[0].pctl); > + phy_softreset(dram); > + move_to_config_state(dram->chan[0].pctl); > + if (data_training(&dram->chan[0])) { > + printf("BW detect error\n"); > + ret = -EINVAL; > + } > + } > + sdram_params->ch[0].bw = bw; > + sdram_params->ch[0].bk = 3; > + > + if (bw == 2) > + writel(6, &axi_bus->ddrconf); > + else > + writel(3, &axi_bus->ddrconf); > + move_to_access_state(dram->chan[0].pctl); > + for (col = 11; col >= 9; col--) { > + writel(0, CONFIG_SYS_SDRAM_BASE); > + addr = CONFIG_SYS_SDRAM_BASE + > + (1 << (col + bw - 1)); > + writel(TEST_PATTEN, addr); > + if ((readl(addr) == TEST_PATTEN) && > + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) > + break; > + } > + if (col == 8) { > + printf("Col detect error\n"); > + ret = -EINVAL; > + goto out; > + } else { > + sdram_params->ch[0].col = col; > + } > + > + writel(10, &axi_bus->ddrconf); > + > + /* Detect row*/ > + for (row = 16; row >= 12; row--) { > + writel(0, CONFIG_SYS_SDRAM_BASE); > + addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); > + writel(TEST_PATTEN, addr); > + if ((readl(addr) == TEST_PATTEN) && > + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) > + break; > + } > + if (row == 11) { > + printf("Row detect error\n"); > + ret = -EINVAL; > + } else { > + sdram_params->ch[0].cs1_row = row; > + sdram_params->ch[0].row_3_4 = 0; > + sdram_params->ch[0].cs0_row = row; > + } > + /* cs detect */ > + writel(0, CONFIG_SYS_SDRAM_BASE); > + writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30)); > + writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4); > + if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && > + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) > + sdram_params->ch[0].rank = 2; > + else > + sdram_params->ch[0].rank = 1; > +out: > + return ret; > +} > + > +static int sdram_init(struct dram_info *dram, > + struct rk322x_sdram_params *sdram_params) > +{ > + int ret; > + > + ret = clk_set_rate(&dram->ddr_clk, > + sdram_params->base.ddr_freq * MHz * 2); > + if (ret < 0) { > + printf("Could not set DDR clock\n"); > + return ret; > + } > + > + phy_pctrl_reset(dram->cru, dram->chan[0].phy); > + phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq); > + pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf); > + phy_cfg(&dram->chan[0], sdram_params); > + writel(POWER_UP_START, &dram->chan[0].pctl->powctl); > + while (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE)) > + ; > + memory_init(&dram->chan[0], sdram_params); > + move_to_access_state(dram->chan[0].pctl); > + ret = dram_cap_detect(dram, sdram_params); > + if (ret) > + goto out; > + dram_cfg_rbc(&dram->chan[0], sdram_params); > + dram_all_config(dram, sdram_params); > +out: > + return ret; > +} > + > +static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev) > +{ > +#if !CONFIG_IS_ENABLED(OF_PLATDATA) > + struct rk322x_sdram_params *params = dev_get_platdata(dev); > + const void *blob = gd->fdt_blob; > + int node = dev_of_offset(dev); > + int ret; > + > + params->num_channels = 1; > + > + ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", > + (u32 *)¶ms->pctl_timing, > + sizeof(params->pctl_timing) / sizeof(u32)); > + if (ret) { > + printf("%s: Cannot read rockchip,pctl-timing\n", __func__); > + return -EINVAL; > + } > + ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", > + (u32 *)¶ms->phy_timing, > + sizeof(params->phy_timing) / sizeof(u32)); > + if (ret) { > + printf("%s: Cannot read rockchip,phy-timing\n", __func__); > + return -EINVAL; > + } > + ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", > + (u32 *)¶ms->base, > + sizeof(params->base) / sizeof(u32)); > + if (ret) { > + printf("%s: Cannot read rockchip,sdram-params\n", __func__); > + return -EINVAL; > + } > + ret = regmap_init_mem(dev, ¶ms->map); > + if (ret) > + return ret; > +#endif > + > + return 0; > +} > +#endif /* CONFIG_TPL_BUILD */ > + > +#if CONFIG_IS_ENABLED(OF_PLATDATA) > +static int conv_of_platdata(struct udevice *dev) > +{ > + struct rk322x_sdram_params *plat = dev_get_platdata(dev); > + struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat; > + int ret; > + > + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, > + sizeof(plat->pctl_timing)); > + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, > + sizeof(plat->phy_timing)); > + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); > + > + plat->num_channels = 1; > + ret = regmap_init_mem_platdata(dev, of_plat->reg, > + ARRAY_SIZE(of_plat->reg) / 2, > + &plat->map); > + if (ret) > + return ret; > + > + return 0; > +} > +#endif > + > +static int rk322x_dmc_probe(struct udevice *dev) > +{ > +#ifdef CONFIG_TPL_BUILD > + struct rk322x_sdram_params *plat = dev_get_platdata(dev); > + int ret; > + struct udevice *dev_clk; > +#endif > + struct dram_info *priv = dev_get_priv(dev); > + > + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); > +#ifdef CONFIG_TPL_BUILD > +#if CONFIG_IS_ENABLED(OF_PLATDATA) > + ret = conv_of_platdata(dev); > + if (ret) > + return ret; > +#endif > + > + priv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); > + priv->chan[0].pctl = regmap_get_range(plat->map, 0); > + priv->chan[0].phy = regmap_get_range(plat->map, 1); > + ret = rockchip_get_clk(&dev_clk); > + if (ret) > + return ret; > + priv->ddr_clk.id = CLK_DDR; > + ret = clk_request(dev_clk, &priv->ddr_clk); > + if (ret) > + return ret; > + > + priv->cru = rockchip_get_cru(); > + if (IS_ERR(priv->cru)) > + return PTR_ERR(priv->cru); > + ret = sdram_init(priv, plat); > + if (ret) > + return ret; > +#else > + priv->info.base = CONFIG_SYS_SDRAM_BASE; > + priv->info.size = rockchip_sdram_size( > + (phys_addr_t)&priv->grf->os_reg[2]); > +#endif > + > + return 0; > +} > + > +static int rk322x_dmc_get_info(struct udevice *dev, struct ram_info *info) > +{ > + struct dram_info *priv = dev_get_priv(dev); > + > + *info = priv->info; > + > + return 0; > +} > + > +static struct ram_ops rk322x_dmc_ops = { > + .get_info = rk322x_dmc_get_info, > +}; > + > +static const struct udevice_id rk322x_dmc_ids[] = { > + { .compatible = "rockchip,rk3228-dmc" }, > + { } > +}; > + > +U_BOOT_DRIVER(dmc_rk322x) = { > + .name = "rockchip_rk322x_dmc", > + .id = UCLASS_RAM, > + .of_match = rk322x_dmc_ids, > + .ops = &rk322x_dmc_ops, > +#ifdef CONFIG_TPL_BUILD > + .ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata, > +#endif > + .probe = rk322x_dmc_probe, > + .priv_auto_alloc_size = sizeof(struct dram_info), > +#ifdef CONFIG_TPL_BUILD > + .platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params), > +#endif > +}; > + > -- > 1.9.1 > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot