Hi,
With the two attached U-Boot patches plus the dts one I get the
following on imx6qp wandboard:
U-Boot SPL 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41)
Trying to boot from MMC1
U-Boot 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41 -0300)
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
I2C: ready
DRAM: 2 GiB
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1
No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
Board: Wandboard rev D1
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot/boot.scr
336 bytes read in 69 ms (3.9 KiB/s)
## Executing script at 12000000
38550 bytes read in 83 ms (453.1 KiB/s)
6378872 bytes read in 367 ms (16.6 MiB/s)
## Flattened Device Tree blob at 18000000
Booting using the fdt blob at 0x18000000
Using Device Tree in place at 18000000, end 1800c695
(Hangs here)
A imx6q wandboard revd1 can boot well though.
Looks like an U-Boot issue. I have also tried booting a dtb + zImage
from the Technexion kernel with the same result.
I am using the very same DDR init from Technexion U-Boot, so not sure
why imx6qp wandboard is not lauching the kernel.
If you have any ideas, please met me know.
Thanks,
Fabio Estevam
From 07a03861d527fdff7adc38b6ab6612f7cc5ff828 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.este...@nxp.com>
Date: Wed, 20 Sep 2017 18:27:46 -0300
Subject: [PATCH v2 1/2] wandboard: Add support for the latest revd1 revision
Latest wandboard hardware revision is revd1, which brings the following
new features:
- PFUZE100 PMIC
- AR8035 Ethernet PHY
- Upgrade Wifi/BT chip to BCM4339/BCM43430.
The detection mechanism is to probe the PMIC and when it is
found, then the revision of the board is revd1.
As the detection is done via PMIC, we need to print the board version
at a later stage via CONFIG_DISPLAY_BOARDINFO_LATE and also need
to disable CONFIG_DISPLAY_BOARDINFO, which is done much earlier.
Make the necessary adjustments for the AR8035 PHY to work on revd1.
Based on Richard Hu's work from Technexion's U-Boot tree.
Signed-off-by: Fabio Estevam <fabio.este...@nxp.com>
---
Changes since v1:
- Fix typo in commit log (Wifi/BT)
board/wandboard/wandboard.c | 110 +++++++++++++++++++++++++++++++++++++++++---
configs/wandboard_defconfig | 1 +
include/configs/wandboard.h | 11 +++++
3 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index adfcf48..14dd378 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -30,6 +30,8 @@
#include <phy.h>
#include <input.h>
#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,8 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
+#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
#define REV_DETECTION IMX_GPIO_NR(2, 28)
+static bool with_pmic;
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -107,6 +112,11 @@ static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
+static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
+ /* AR8035 POWER */
+ IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
static iomux_v3_cfg_t const rev_detection_pad[] = {
IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
@@ -120,6 +130,14 @@ static void setup_iomux_enet(void)
{
SETUP_IOMUX_PADS(enet_pads);
+ if (with_pmic) {
+ SETUP_IOMUX_PADS(enet_ar8035_power_pads);
+ /* enable AR8035 POWER */
+ gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
+ }
+ /* wait until 3.3V of PHY and clock become stable */
+ mdelay(10);
+
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
mdelay(10);
@@ -192,6 +210,7 @@ int board_mmc_init(bd_t *bis)
static int ar8031_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
+ int mask;
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
@@ -199,7 +218,12 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
+ if (with_pmic)
+ mask = 0xffe7; /* AR8035 */
+ else
+ mask = 0xffe3; /* AR8031 */
+
+ val &= mask;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
@@ -257,6 +281,40 @@ struct i2c_pads_info mx6dl_i2c2_pad_info = {
}
};
+struct i2c_pads_info mx6q_i2c3_pad_info = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+};
+
+struct i2c_pads_info mx6dl_i2c3_pad_info = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+};
+
static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
@@ -388,6 +446,31 @@ int board_early_init_f(void)
return 0;
}
+#define PMIC_I2C_BUS 2
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ u32 reg;
+
+ /* configure PFUZE100 PMIC */
+ power_pfuze100_init(PMIC_I2C_BUS);
+ p = pmic_get("PFUZE100");
+ if (p && !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ with_pmic = true;
+
+ /* Set VGEN2 to 1.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN2VOL, ®);
+ reg &= ~(LDO_VOL_MASK);
+ reg |= (LDOA_1_50V | (1 << (LDO_EN)));
+ pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
+ }
+
+ return 0;
+}
+
/*
* Do not overwrite the console
* Use always serial for U-Boot console
@@ -417,6 +500,14 @@ static bool is_revc1(void)
return false;
}
+static bool is_revd1(void)
+{
+ if (with_pmic)
+ return true;
+ else
+ return false;
+}
+
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
@@ -429,7 +520,9 @@ int board_late_init(void)
else
env_set("board_rev", "MX6DL");
- if (is_revc1())
+ if (is_revd1())
+ env_set("board_name", "D1");
+ else if (is_revc1())
env_set("board_name", "C1");
else
env_set("board_name", "B1");
@@ -442,20 +535,23 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#if defined(CONFIG_VIDEO_IPUV3)
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
- if (is_mx6dq())
+ if (is_mx6dq()) {
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
- else
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
+ } else {
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-#endif
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
+ }
return 0;
}
int checkboard(void)
{
- if (is_revc1())
+ if (is_revd1())
+ puts("Board: Wandboard rev D1\n");
+ else if (is_revc1())
puts("Board: Wandboard rev C1\n");
else
puts("Board: Wandboard rev B1\n");
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 9765f13..8097e6e 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 3ba4c29..ba88d02 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -13,6 +13,7 @@
#include "mx6_common.h"
#include "imx6_spl.h"
+#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6
@@ -44,6 +45,12 @@
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
/* MMC Configuration */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
@@ -102,6 +109,10 @@
"fi; " \
"fi\0" \
"findfdt="\
+ "if test $board_name = D1 && test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \
+ "if test $board_name = D1 && test $board_rev = MX6DL ; then " \
+ "setenv fdtfile imx6dl-wandboard-revd1.dtb; fi; " \
"if test $board_name = C1 && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-wandboard.dtb; fi; " \
"if test $board_name = C1 && test $board_rev = MX6DL ; then " \
--
2.7.4
From 844048a77f43ea7e2e85b5aff9730fa61868c729 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.este...@nxp.com>
Date: Wed, 20 Sep 2017 18:55:39 -0300
Subject: [PATCH v2 2/2] wandboard: Add support for the MX6QP variant
Add support for the latest MX6QP wandboard variant.
Based on Richard Hu's work from Technexion's U-Boot tree.
Signed-off-by: Fabio Estevam <fabio.este...@nxp.com>
---
Changes since v1:
- None
arch/arm/include/asm/arch-mx6/imx-regs.h | 3 +
board/wandboard/spl.c | 133 ++++++++++++++++++++++++++++++-
board/wandboard/wandboard.c | 6 +-
include/configs/wandboard.h | 2 +
4 files changed, 141 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 86e2670..624ccec 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -346,6 +346,9 @@
#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#endif
+
+#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
+
/* Only for i.MX6SX */
#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 00c75d0..3619cf6 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX6DQ_DRIVE_STRENGTH 0x30
#define IMX6SDL_DRIVE_STRENGTH 0x28
+#define IMX6QP_DRIVE_STRENGTH 0x28
/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
@@ -266,9 +267,139 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
+static void spl_dram_init_imx6qp_lpddr3(void)
+{
+ /* DDR IO TYPE */
+ writel(0x000C0000, IOMUXC_BASE_ADDR + 0x798);
+ writel(0x00000000, IOMUXC_BASE_ADDR + 0x758);
+ /* Clock */
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x588);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x594);
+ /* Address */
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x56c);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x578);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x74c);
+ /* Control */
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x57c);
+ writel(0x00000000, IOMUXC_BASE_ADDR + 0x58c);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x59c);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5a0);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x78c);
+ /* Data Strobe */
+ writel(0x00020000, IOMUXC_BASE_ADDR + 0x750);
+
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5a8);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b0);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x524);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x51c);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x518);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x50c);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b8);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5c0);
+ /* Data */
+ writel(0x00020000, IOMUXC_BASE_ADDR + 0x774);
+
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x784);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x788);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x794);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x79c);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a0);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a4);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a8);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x748);
+
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5ac);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b4);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x528);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x520);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x514);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x510);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5bc);
+ writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5c4);
+
+ /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
+ writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+
+ /* Calibrations - ZQ */
+ writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
+ /* write leveling */
+ writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
+ writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
+ writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
+ writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
+ /*
+ * DQS gating, read delay, write delay calibration values
+ * based on calibration compare of 0x00ffff00
+ */
+ writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
+ writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
+ writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
+ writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
+
+ writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
+ writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
+
+ writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
+ writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
+
+ writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
+ writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
+ writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
+ writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
+ writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
+ writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
+ writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
+ writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
+
+ writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
+ writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
+
+ writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
+ writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
+ /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
+ writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
+ writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
+ writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
+ writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
+ writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
+
+ writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
+ writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+ writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
+ writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
+ writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
+
+ writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
+ writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
+ writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
+
+ /* add NOC DDR configuration */
+ writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
+ writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
+ writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
+ writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
+ writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
+ writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
+
+ writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
+ writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
+ writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
+ writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
+ writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
+
+ writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
+ writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
+ writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
+ writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
+ writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
+ writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
+}
+
static void spl_dram_init(void)
{
- if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+ if (is_mx6dqp()) {
+ spl_dram_init_imx6qp_lpddr3();
+ } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
} else if (is_cpu_type(MXC_CPU_MX6DL)) {
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 14dd378..34bb3b6 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -515,7 +515,9 @@ int board_late_init(void)
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (is_mx6dq())
+ if (is_mx6dqp())
+ env_set("board_rev", "MX6QP");
+ else if (is_mx6dq())
env_set("board_rev", "MX6Q");
else
env_set("board_rev", "MX6DL");
@@ -536,7 +538,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
- if (is_mx6dq()) {
+ if (is_mx6dq() || is_mx6dqp()) {
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
} else {
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index ba88d02..8fdfc02 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -109,6 +109,8 @@
"fi; " \
"fi\0" \
"findfdt="\
+ "if test $board_name = D1 && test $board_rev = MX6QP ; then " \
+ "setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \
"if test $board_name = D1 && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \
"if test $board_name = D1 && test $board_rev = MX6DL ; then " \
--
2.7.4
From ef2646abbc94cebee48b30e5b22c03ab117f139c Mon Sep 17 00:00:00 2001
From: Fabio Estevam <feste...@gmail.com>
Date: Wed, 27 Sep 2017 10:11:22 -0300
Subject: [PATCH] wandboardupdate
Signed-off-by: Fabio Estevam <feste...@gmail.com>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6dl-wandboard-revd1.dts | 22 +++
arch/arm/boot/dts/imx6q-wandboard-revd1.dts | 26 ++++
arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi | 196 +++++++++++++++++++++++++
arch/arm/boot/dts/imx6qp-wandboard-revd1.dts | 22 +++
5 files changed, 269 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
create mode 100644 arch/arm/boot/dts/imx6q-wandboard-revd1.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
create mode 100644 arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 097a1e5..7a540ff 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -396,6 +396,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-udoo.dtb \
imx6dl-wandboard.dtb \
imx6dl-wandboard-revb1.dtb \
+ imx6dl-wandboard-revd1.dtb \
imx6q-apalis-eval.dtb \
imx6q-apalis-ixora.dtb \
imx6q-apalis-ixora-v1.1.dtb \
@@ -453,11 +454,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-utilite-pro.dtb \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
+ imx6q-wandboard-revd1.dtb \
imx6q-zii-rdu2.dtb \
imx6qp-nitrogen6_max.dtb \
imx6qp-nitrogen6_som2.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb \
+ imx6qp-wandboard-revd1.dtb \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
new file mode 100644
index 0000000..aa4d4fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.este...@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-wandboard-revd1.dtsi"
+
+/ {
+ model = "Wandboard i.MX6 Dual Lite Board revD1";
+ compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
+
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
new file mode 100644
index 0000000..e87ddb1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.este...@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-wandboard-revd1.dtsi"
+
+/ {
+ model = "Wandboard i.MX6 Quad Board revD1";
+ compatible = "wand,imx6q-wandboard", "fsl,imx6q";
+
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
new file mode 100644
index 0000000..1ae9696
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi
@@ -0,0 +1,196 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.este...@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "imx6qdl-wandboard.dtsi"
+
+/ {
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ regulator-name = "ETH_PHY";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&fec {
+ phy-supply = <®_eth_phy>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6qdl-wandboard {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+ >;
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
new file mode 100644
index 0000000..7df5d96
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.este...@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+#include "imx6qp.dtsi"
+#include "imx6qdl-wandboard-revd1.dtsi"
+
+/ {
+ model = "Wandboard i.MX6 QuadPlus Board revD1";
+ compatible = "wand,imx6qp-wandboard", "fsl,imx6qp";
+
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+};
--
2.7.4
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