On 10/03/2017 11:08 AM, Andy Shevchenko wrote: > On Tue, 2017-10-03 at 13:05 +0530, Faiz Abbas wrote: >> Hi, >> >> On Tuesday 19 September 2017 04:45 PM, Faiz Abbas wrote: >>> A flush of the cache is required before any DMA access can take >>> place. >>> The minimum size that can be flushed from the cache is one cache >>> line >>> size. Therefore, any buffer allocated for DMA should be in multiples >>> of cache line size. >>> >>> Thus, allocate memory for ep0_trb in multiples of cache line size. >>> >>> Also, when local variable trb is assigned to dwc->ep0_trb[1] and >>> used >>> to flush cache, it leads to cache misaligned messages as only the >>> base >>> address dwc->ep0_trb is cache aligned. >>> >>> Therefore, flush cache using ep0_trb_addr which is always cache >>> aligned. >>> >>> Signed-off-by: Faiz Abbas <faiz_ab...@ti.com> >> >> Gentle ping. > > Can you resend with Felipe Balbi included?
You can just reply to the original email and add people to CC of that reply instead of resending ? > And I'm not sure Vincent is anyhow related to this anymore (or even > works with us). > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
