Hi all,
This is a patch to fix the NUMONYX's M29W128GL cfi detection bug in my
Lite5200B based custom board. I thing I's only a starting point for a
more formal patch valid for any kind of architecture (big and little
endian) and flash layout (I've only check it in a 16x portwitdh 8x
chipwitch).
I'm not a CFI flash expert and any feedback about this issue will be
welcomed.
TIA,
--- cfi_flash_old.c 2009-12-09 18:25:44.000000000 +0100
+++ cfi_flash_new.c 2009-12-17 10:28:00.000000000 +0100
@@ -214,6 +214,10 @@ static void flash_make_cmd(flash_info_t
val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1);
#endif
cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
+ if(info->cfi_fixup & CFI_NUMONYX_FIXUP) {
+ if(cp_offset & 1)
+ cp[cp_offset] = 0x00;
+ }
}
}
@@ -266,7 +270,10 @@ static inline uchar flash_read_uchar (fl
#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
retval = flash_read8(cp);
#else
- retval = flash_read8(cp + info->portwidth - 1);
+ if(info->cfi_fixup & CFI_NUMONYX_FIXUP)
+ retval = flash_read8(cp);
+ else
+ retval = flash_read8(cp + info->portwidth - 1);
#endif
flash_unmap (info, 0, offset, cp);
return retval;
@@ -1420,7 +1427,12 @@ static void cmdset_amd_read_jedec_ids(fl
{
ushort bankId = 0;
uchar manuId;
+ uchar portwidth;
+ portwidth = info->portwidth;
+ if(info->chipwidth == FLASH_CFI_8BIT)
+ info->portwidth = FLASH_CFI_8BIT;
+
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
flash_unlock_seq(info, 0);
flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
@@ -1438,14 +1450,14 @@ static void cmdset_amd_read_jedec_ids(fl
switch (info->chipwidth){
case FLASH_CFI_8BIT:
info->device_id = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID);
+ FLASH_OFFSET_DEVICE_ID *
portwidth);
if (info->device_id == 0x7E) {
/* AMD 3-byte (expanded) device ids */
info->device_id2 = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID2);
+ FLASH_OFFSET_DEVICE_ID2 *
portwidth);
info->device_id2 <<= 8;
info->device_id2 |= flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID3);
+ FLASH_OFFSET_DEVICE_ID3 *
portwidth);
}
break;
case FLASH_CFI_16BIT:
@@ -1456,6 +1468,9 @@ static void cmdset_amd_read_jedec_ids(fl
break;
}
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+
+ info->portwidth = portwidth;
+
}
static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
@@ -1582,6 +1597,10 @@ void __flash_cmd_reset(flash_info_t *inf
* that AMD flash roms ignore the Intel command.
*/
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+
+ if(info->cfi_fixup & CFI_NUMONYX_FIXUP)
+ return;
+
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
}
void flash_cmd_reset(flash_info_t *info)
@@ -1646,6 +1665,12 @@ static int flash_detect_cfi (flash_info_
{
debug ("flash detect cfi\n");
+ info->cfi_fixup = 0;
+
+#ifdef CONFIG_FLASH_NUMONYX_FIXUP
+ info->cfi_fixup = CFI_NUMONYX_FIXUP;
+#endif
+
for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
for (info->chipwidth = FLASH_CFI_BY8;
--- flash_old.h 2009-12-10 12:25:41.000000000 +0100
+++ flash_new.h 2009-12-17 10:26:55.000000000 +0100
@@ -55,6 +55,7 @@ typedef struct {
ulong addr_unlock1; /* unlock address 1 for AMD flash roms
*/
ulong addr_unlock2; /* unlock address 2 for AMD flash roms
*/
const char *name; /* human-readable name
*/
+ uchar cfi_fixup;
#endif
} flash_info_t;
@@ -87,6 +88,9 @@ typedef unsigned long flash_sect_t;
/* convert between bit value and numeric value */
#define CFI_FLASH_SHIFT_WIDTH 3
+
+#define CFI_NUMONYX_FIXUP 0x01
+
/* Prototypes */
extern unsigned long flash_init (void);
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