On 11/03/2017 01:07 PM, Karsten Merker wrote:
On Fri, Nov 03, 2017 at 08:56:51AM +0200, Stefan Mavrodiev wrote:From revision J the board uses new phy chip LAN8710. Compared with RTL8201, RA17 pin is TXERR. It has pullup which causes phy not to work. To fix this PA17 is muxed with GMAC function. This makes the pin output-low. Signed-off-by: Stefan Mavrodiev <ste...@olimex.com> --- Changes for v2: - The pin mux is done with Kconfig option - Same option is enable by default for A20-OLinuXino-MICRO boards board/sunxi/gmac.c | 4 ++++ configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 + configs/A20-OLinuXino_MICRO_defconfig | 1 + drivers/net/Kconfig | 8 ++++++++ 4 files changed, 14 insertions(+) diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 69eb8ff..826650c 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -33,7 +33,11 @@ void eth_init_board(void)#ifndef CONFIG_MACH_SUN6I/* Configure pin mux settings for GMAC */ +#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) { +#else for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { +#endif #ifdef CONFIG_RGMII /* skip unused pins in RGMII mode */ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index 2ff2723..43bcea9 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y +CONFIG_SUN7I_GMAC_FORCE_TXERR=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 1a0ad5a..22eacb3 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y +CONFIG_SUN7I_GMAC_FORCE_TXERR=y CONFIG_AXP_ALDO3_VOLT=2800 CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=yHello, wouldn't this break networking on pre-revision-J A20-OLinuXino_MICRO boards? AIUI, the A20-OLinuXino_MICRO before Revision J uses PA17 to control the (low-active) RESETB# line of the RTL8201CP used on the older board revisions, so with this change the PHY on pre-revision-J boards would be held in permanent reset state. AIUI, it would be necessary to have two different defconfigs - the existing defconfig for pre-revision-J boards (without CONFIG_SUN7I_GMAC_FORCE_TXERR) and an additional new one for revision-J-and-newer boards which sets CONFIG_SUN7I_GMAC_FORCE_TXERR=y.
Yes, the boards before rev.J uses this signal as EPHY-RST#, but only as an option. It's disconnected by N/A resistor. So setting this as output-low will not have any unwanted effect. You can see this in this schematic: https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A10-OLinuXino-MICRO/A20-OLINUXINO-MICRO_4GB_Rev_G1.pdf
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index c1ce54e..f9f04e4 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -244,6 +244,14 @@ config SUN7I_GMAC help Enable the support for Sun7i GMAC Ethernet controller+config SUN7I_GMAC_FORCE_TXERR+ bool "Force PA17 as gmac function" + depends on SUN7I_GMAC + help + Some ethernet phys needs TXERR control. Since the GMAC + doesn't have such signal, setting PA17 as GMAC function + makes the pin output low, which enables data transmission. + config SUN4I_EMAC bool "Allwinner Sun4i Ethernet MAC support" depends on DM_ETH Regards, Karsten
Regards, Stefan Mavrodiev _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
