On Thu, Oct 26, 2017 at 01:23:19PM +0200, patrice.chot...@st.com wrote: > From: Patrice Chotard <patrice.chot...@st.com> > > Fix clock division factor initialization for RCC_PLLCFGR > registers. > > PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared, > it's a forbidden value. So update RCC_PLLCFGR using > clrsetbits_le32() to set only necessary bits fields. > > Signed-off-by: Patrice Chotard <patrice.chot...@st.com> > Reviewed-by: Simon Glass <s...@chromium.org>
Applied to u-boot/master, thanks! -- Tom
signature.asc
Description: PGP signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
