On Tue, 2017-11-21 at 18:35 +0000, York Sun wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 11/21/2017 10:20 AM, Joakim Tjernlund wrote: > > On Tue, 2017-11-21 at 18:04 +0000, York Sun wrote: > > > > > > > > > On 11/21/2017 09:52 AM, Joakim Tjernlund wrote: > > > > On Tue, 2017-11-21 at 17:45 +0000, York Sun wrote: > > > > > > > > > > On 11/21/2017 09:41 AM, Joakim Tjernlund wrote: > > > > > > On Tue, 2017-11-21 at 17:32 +0000, York Sun wrote: > > > > > > > CAUTION: This email originated from outside of the organization. > > > > > > > Do not click links or open attachments unless you recognize the > > > > > > > sender and know the content is safe. > > > > > > > > > > > > > > > > > > > > > On 11/21/2017 09:29 AM, Joakim Tjernlund wrote: > > > > > > > > On Tue, 2017-11-21 at 17:23 +0000, York Sun wrote: > > > > > > > > > CAUTION: This email originated from outside of the > > > > > > > > > organization. Do not click links or open attachments unless > > > > > > > > > you recognize the sender and know the content is safe. > > > > > > > > > > > > > > > > > > > > > > > > > > > On 11/21/2017 09:18 AM, Joakim Tjernlund wrote: > > > > > > > > > > On Tue, 2017-09-12 at 19:56 +0200, Joakim Tjernlund wrote: > > > > > > > > > > > Most FSL PCIe controllers expects 333 MHz PCI reference > > > > > > > > > > > clock. > > > > > > > > > > > This clock is derived from the CCB but in many cases the > > > > > > > > > > > ref. > > > > > > > > > > > clock is not 333 MHz and a divisor needs to be configured. > > > > > > > > > > > > > > > > > > > > > > This adds PEX_CCB_DIV #define which can be defined for > > > > > > > > > > > each > > > > > > > > > > > type of CPU/platform. > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Joakim Tjernlund > > > > > > > > > > > <joakim.tjernl...@infinera.com> > > > > > > > > > > > --- > > > > > > > > > > > drivers/pci/fsl_pci_init.c | 6 ++++++ > > > > > > > > > > > 1 file changed, 6 insertions(+) > > > > > > > > > > > > > > > > > > > > > > diff --git a/drivers/pci/fsl_pci_init.c > > > > > > > > > > > b/drivers/pci/fsl_pci_init.c > > > > > > > > > > > index 52792dcd59..4d00b3f26c 100644 > > > > > > > > > > > --- a/drivers/pci/fsl_pci_init.c > > > > > > > > > > > +++ b/drivers/pci/fsl_pci_init.c > > > > > > > > > > > @@ -322,6 +322,12 @@ void fsl_pci_init(struct > > > > > > > > > > > pci_controller *hose, struct fsl_pci_info *pci_info) > > > > > > > > > > > > > > > > > > > > > > pci_setup_indirect(hose, cfg_addr, cfg_data); > > > > > > > > > > > > > > > > > > > > > > +#ifdef PEX_CCB_DIV > > > > > > > > > > > + /* Configure the PCIE controller core clock ratio */ > > > > > > > > > > > + pci_hose_write_config_dword(hose, dev, 0x440, > > > > > > > > > > > + ((gd->bus_clk / 1000000) > > > > > > > > > > > * > > > > > > > > > > > + (16 / PEX_CCB_DIV)) / > > > > > > > > > > > 333); > > > > > > > > > > > +#endif > > > > > > > > > > > > I took another look at this patch. Would it be appropriate to alway > > > write to this register with correct clock? > > > > I sure hope so, the docs I have only mentions this reg having a default > > value which > > needs to be changed in most cases I guess. > > > The only case we don't need to set this register is when the actual > clock is 333MHz. I wonder why we didn't have a problem so far. Maybe we > just didn't realize it.
Have you tried higher PCI speeds? I remember a board we had didn't work with higher speeds so we settled for less than max. Don't hav the board handy now. Jocke _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
