This short series fixes a few issues related to our caching code - with regards to DMA coherence, instruction cache coherence & systems with no caches at all.
Applies atop u-boot-mips/next as of d7d9fc01a4ef ("Update Paul Burton's email address"). Paul Burton (3): MIPS: Ensure cache ops complete in cache maintenance functions MIPS: Clear instruction hazards in flush_cache() MIPS: Break out of cache loops for unimplemented caches arch/mips/include/asm/system.h | 13 +++++++++++++ arch/mips/lib/cache.c | 30 ++++++++++++++++++++++-------- 2 files changed, 35 insertions(+), 8 deletions(-) -- 2.15.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot