On Thu, 9 Nov 2017, David Wu wrote:
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
See below for requested changes.
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
index e87267d..5fd27cd 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -239,6 +239,16 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru,
uint clk_general_rate,
return DIV_TO_RATE(src_rate, div) / 2;
}
+static int rk322x_mac_set_clk(struct rk322x_cru *cru,
+ int periph, uint freq)
+{
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5),
+ BIT(5));
Please use a symbolic constant for BIT(5).
If this is the input/output selection for the MAC clk and covered by
'clock_in_out = "input";' in the DTS, then the DTS should be consulted
before assuming a specific setting here.
+
+ return 0;
+}
+
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
int periph, uint freq)
{
@@ -352,6 +362,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong
rate)
case CLK_DDR:
new_rate = rk322x_ddr_set_clk(priv->cru, rate);
break;
+ case SCLK_MAC:
+ new_rate = rk322x_mac_set_clk(priv->cru, clk->id, rate);
+ break;
default:
return -ENOENT;
}
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