Hi Peng,
On 07/12/2017 10:13, Peng Fan wrote:
> Hi Stefano,
>
> On Thu, Dec 07, 2017 at 09:52:46AM +0100, Stefano Babic wrote:
>> Hi Peng,
>>
>> On 04/12/2017 05:31, Peng Fan wrote:
>>> Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
>>> firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
>>> DRAM.
>>>
>>> The boot log:
>>> "
>>> U-Boot SPL 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31)
>>> PMIC: PFUZE100 ID=0x10
>>> check ddr4_pmu_train_imem code
>>> check ddr4_pmu_train_imem code pass
>>> check ddr4_pmu_train_dmem code
>>> check ddr4_pmu_train_dmem code pass
>>> PLL bypass to 100MTS setting done
>>> Training PASS
>>> PLL bypass to 400MTS setting done
>>> Training PASS
>>> Training PASS
>>> check ddr4_pmu_train_imem code
>>> check ddr4_pmu_train_imem code pass
>>> check ddr4_pmu_train_dmem code
>>> check ddr4_pmu_train_dmem code pass
>>> Training PASS
>>> Normal Boot
>>> Trying to boot from MMC2
>>>
>>> U-Boot 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31 +0800)
>>>
>>> CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz
>>> Reset cause: POR
>>> Model: Freescale i.MX8MQ EVK
>>> DRAM: 3 GiB
>>> MMC: FSL_SDHC: 0, FSL_SDHC: 1
>>> Using default environment
>>>
>>> In: serial
>>> Out: serial
>>> Err: serial
>>> Net: No ethernet found.
>>> Hit any key to stop autoboot: 0
>>> "
>>>
>>> Signed-off-by: Peng Fan <peng....@nxp.com>
>>> ---
>>> arch/arm/dts/Makefile | 2 +
>>> arch/arm/dts/fsl-imx8mq-evk.dts | 424
>>> ++++++++++++++++++++++++++++++++++
>>> arch/arm/mach-imx/mx8m/Kconfig | 12 +
>>> board/freescale/mx8mq_evk/Kconfig | 12 +
>>> board/freescale/mx8mq_evk/Makefile | 11 +
>>> board/freescale/mx8mq_evk/README | 38 +++
>>> board/freescale/mx8mq_evk/mx8mq_evk.c | 156 +++++++++++++
>>> board/freescale/mx8mq_evk/spl.c | 233 +++++++++++++++++++
>>> configs/mx8mq_evk_defconfig | 28 +++
>>> include/configs/mx8mq_evk.h | 265 +++++++++++++++++++++
>>> 10 files changed, 1181 insertions(+)
>>> create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
>>> create mode 100644 board/freescale/mx8mq_evk/Kconfig
>>> create mode 100644 board/freescale/mx8mq_evk/Makefile
>>> create mode 100644 board/freescale/mx8mq_evk/README
>>> create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
>>> create mode 100644 board/freescale/mx8mq_evk/spl.c
>>> create mode 100644 configs/mx8mq_evk_defconfig
>>> create mode 100644 include/configs/mx8mq_evk.h
>>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index cd540e99ea..d459755904 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -381,6 +381,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
>>>
>>> dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>>>
>>> +dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb
>>> +
>>> dtb-$(CONFIG_RCAR_GEN3) += \
>>> r8a7795-h3ulcb.dtb \
>>> r8a7795-salvator-x.dtb \
>>> diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts
>>> b/arch/arm/dts/fsl-imx8mq-evk.dts
>>> new file mode 100644
>>> index 0000000000..f0aa3485e6
>>> --- /dev/null
>>> +++ b/arch/arm/dts/fsl-imx8mq-evk.dts
>>> @@ -0,0 +1,424 @@
>>> +/*
>>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>>> + * Copyright 2017 NXP
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License
>>> + * as published by the Free Software Foundation; either version 2
>>> + * of the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +/* First 128KB is for PSCI ATF. */
>>> +/memreserve/ 0x40000000 0x00020000;
>>> +
>>> +#include "fsl-imx8mq.dtsi"
>>> +
>>> +/ {
>>> + model = "Freescale i.MX8MQ EVK";
>>> + compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
>>> +
>>> + chosen {
>>> + bootargs = "console=ttymxc0,115200
>>> earlycon=ec_imx6q,0x30860000,115200";
>>> + };
>>> +
>>> + regulators {
>>> + compatible = "simple-bus";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + reg_usdhc2_vmmc: usdhc2_vmmc {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "VSD_3V3";
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>>> + enable-active-high;
>>> + };
>>> + };
>>> +
>>> + pwmleds {
>>> + compatible = "pwm-leds";
>>> +
>>> + ledpwm2 {
>>> + label = "PWM2";
>>> + pwms = <&pwm2 0 50000>;
>>> + max-brightness = <255>;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&iomuxc {
>>> + pinctrl-names = "default";
>>> +
>>> + imx8mq-evk {
>>> + pinctrl_fec1: fec1grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
>>> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
>>> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
>>> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
>>> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
>>> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>>> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>>> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>>> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>>> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>>> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>>> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>>> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
>>> 0x91
>>> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
>>> 0x1f
>>> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>>> + >;
>>> + };
>>> +
>>> + pinctrl_i2c1: i2c1grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
>>> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>>> + >;
>>> + };
>>> +
>>> + pinctrl_i2c2: i2c2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
>>> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>>> + >;
>>> + };
>>> +
>>> + pinctrl_pwm2: pwm2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
>>> + >;
>>> + };
>>> +
>>> + pinctrl_qspi: qspigrp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
>>> + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>>> +
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc1: usdhc1grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
>>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
>>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
>>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
>>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
>>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
>>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
>>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
>>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
>>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>>> + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2: usdhc2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
>>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
>>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
>>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
>>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
>>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_sai2: sai2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
>>> + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
>>> + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
>>> + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
>>> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>>> + >;
>>> + };
>>> +
>>> + pinctrl_wdog: wdoggrp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>>> + >;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&fec1 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_fec1>;
>>> + phy-mode = "rgmii-id";
>>> + phy-handle = <ðphy0>;
>>> + fsl,magic-packet;
>>> + status = "okay";
>>> +
>>> + mdio {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + ethphy0: ethernet-phy@0 {
>>> + compatible = "ethernet-phy-ieee802.3-c22";
>>> + reg = <0>;
>>> + at803x,led-act-blind-workaround;
>>> + at803x,eee-disabled;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&i2c1 {
>>> + clock-frequency = <100000>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_i2c1>;
>>> + status = "okay";
>>> +
>>> + pmic: pfuze100@08 {
>>> + compatible = "fsl,pfuze100";
>>> + reg = <0x08>;
>>> +
>>> + regulators {
>>> + sw1a_reg: sw1ab {
>>> + regulator-min-microvolt = <300000>;
>>> + regulator-max-microvolt = <1875000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw1c_reg: sw1c {
>>> + regulator-min-microvolt = <300000>;
>>> + regulator-max-microvolt = <1875000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw2_reg: sw2 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw3a_reg: sw3ab {
>>> + regulator-min-microvolt = <400000>;
>>> + regulator-max-microvolt = <1975000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw4_reg: sw4 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + swbst_reg: swbst {
>>> + regulator-min-microvolt = <5000000>;
>>> + regulator-max-microvolt = <5150000>;
>>> + };
>>> +
>>> + snvs_reg: vsnvs {
>>> + regulator-min-microvolt = <1000000>;
>>> + regulator-max-microvolt = <3000000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vref_reg: vrefddr {
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen1_reg: vgen1 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <1550000>;
>>> + };
>>> +
>>> + vgen2_reg: vgen2 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <1550000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen3_reg: vgen3 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen4_reg: vgen4 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen5_reg: vgen5 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen6_reg: vgen6 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + };
>>> + };
>>> + };
>>> +};
>>> +
>>> +&i2c2 {
>>> + clock-frequency = <100000>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_i2c2>;
>>> + status = "disabled";
>>> +};
>>> +
>>> +&pwm2 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_pwm2>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&lcdif {
>>> + status = "okay";
>>> + disp-dev = "mipi_dsi_northwest";
>>> + display = <&display0>;
>>> +
>>> + display0: display@0 {
>>> + bits-per-pixel = <24>;
>>> + bus-width = <24>;
>>> +
>>> + display-timings {
>>> + native-mode = <&timing0>;
>>> + timing0: timing0 {
>>> + clock-frequency = <9200000>;
>>> + hactive = <480>;
>>> + vactive = <272>;
>>> + hfront-porch = <8>;
>>> + hback-porch = <4>;
>>> + hsync-len = <41>;
>>> + vback-porch = <2>;
>>> + vfront-porch = <4>;
>>> + vsync-len = <10>;
>>> +
>>> + hsync-active = <0>;
>>> + vsync-active = <0>;
>>> + de-active = <1>;
>>> + pixelclk-active = <0>;
>>> + };
>>> + };
>>> + };
>>> +};
>>> +
>>> +&qspi {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_qspi>;
>>> + status = "okay";
>>> +
>>> + flash0: n25q256a@0 {
>>> + reg = <0>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + compatible = "micron,n25q256a";
>>> + spi-max-frequency = <29000000>;
>>> + spi-nor,ddr-quad-read-dummy = <6>;
>>> + };
>>> +};
>>> +
>>> +&usdhc1 {
>>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>> + pinctrl-0 = <&pinctrl_usdhc1>;
>>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>>> + bus-width = <8>;
>>> + non-removable;
>>> + status = "okay";
>>> +};
>>> +
>>> +&usdhc2 {
>>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>>> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
>>> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
>>> + bus-width = <4>;
>>> + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
>>> + vmmc-supply = <®_usdhc2_vmmc>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&wdog1 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_wdog>;
>>> + fsl,ext-reset-output;
>>> + status = "okay";
>>> +};
>>> diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
>>> index 3a84c2f2b0..e3b57b7915 100644
>>> --- a/arch/arm/mach-imx/mx8m/Kconfig
>>> +++ b/arch/arm/mach-imx/mx8m/Kconfig
>>> @@ -7,4 +7,16 @@ config MX8M
>>> config SYS_SOC
>>> default "mx8m"
>>>
>>> +choice
>>> + prompt "NXP i.MX8M board select"
>>> + optional
>>> +
>>> +config TARGET_MX8MQ_EVK
>>> + bool "mx8mq_evk"
>>> + select MX8M
>>> +
>>> +endchoice
>>> +
>>> +source "board/freescale/mx8mq_evk/Kconfig"
>>> +
>>> endif
>>> diff --git a/board/freescale/mx8mq_evk/Kconfig
>>> b/board/freescale/mx8mq_evk/Kconfig
>>> new file mode 100644
>>> index 0000000000..4e23002803
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/Kconfig
>>> @@ -0,0 +1,12 @@
>>> +if TARGET_MX8MQ_EVK
>>> +
>>> +config SYS_BOARD
>>> + default "mx8mq_evk"
>>> +
>>> +config SYS_VENDOR
>>> + default "freescale"
>>> +
>>> +config SYS_CONFIG_NAME
>>> + default "mx8mq_evk"
>>> +
>>> +endif
>>> diff --git a/board/freescale/mx8mq_evk/Makefile
>>> b/board/freescale/mx8mq_evk/Makefile
>>> new file mode 100644
>>> index 0000000000..60c99d4194
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/Makefile
>>> @@ -0,0 +1,11 @@
>>> +#
>>> +# Copyright 2017 NXP
>>> +#
>>> +# SPDX-License-Identifier: GPL-2.0+
>>> +#
>>> +
>>> +obj-y += mx8mq_evk.o
>>> +
>>> +ifdef CONFIG_SPL_BUILD
>>> +obj-y += spl.o
>>> +endif
>>> diff --git a/board/freescale/mx8mq_evk/README
>>> b/board/freescale/mx8mq_evk/README
>>> new file mode 100644
>>> index 0000000000..6be5f51a22
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/README
>>> @@ -0,0 +1,38 @@
>>> +U-Boot for the NXP i.MX8MQ EVK board
>>> +
>>> +Quick Start
>>> +====================
>>> +- Build the ARM Trusted firmware binary
>>> +- Build U-Boot
>>> +- Generate flash.bin using imx-mkimage
>>> +- Boot
>>> +
>>> +Build the ARM Trusted firmware
>>> +====================
>>> +$ make PLAT=imx8mq bl31
>>> +
>>> +Build U-Boot
>>> +====================
>>> +$ export ARCH=arm64
>>> +$ export CROSS_COMPILE=aarch64-poky-linux-
>>> +$ make mx8mq_evk_defconfig
>>> +$ make
>>> +
>>> +Generate flash.bin using imx-mkimage
>>> +====================
>>> +Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to
>>> + imx-mkimage/iMX8M
>>> +Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin
>>> + lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to
>>> + imx-mkimage/iMX8M
>>> +If you want to run with HDMI, copy signed_hdmi_imx8m.bin to
>>> imx-mkimage/iMX8M
>>> +
>>> +make SOC=iMX8M flash_spl_uboot or make SOC=iMX8M flash_hdmi_spl_uboot to
>>> +generate flash.bin.
>>> +
>>> +Burn the flash.bin to MicroSD card offset 33KB
>>> +$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
>>> +
>>> +Boot
>>> +====================
>>> +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
>>> diff --git a/board/freescale/mx8mq_evk/mx8mq_evk.c
>>> b/board/freescale/mx8mq_evk/mx8mq_evk.c
>>> new file mode 100644
>>> index 0000000000..e31678efb7
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/mx8mq_evk.c
>>> @@ -0,0 +1,156 @@
>>> +/*
>>> + * Copyright 2017 NXP
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <malloc.h>
>>> +#include <errno.h>
>>> +#include <asm/io.h>
>>> +#include <miiphy.h>
>>> +#include <netdev.h>
>>> +#include <asm/mach-imx/iomux-v3.h>
>>> +#include <asm-generic/gpio.h>
>>> +#include <fsl_esdhc.h>
>>> +#include <mmc.h>
>>> +#include <asm/arch/mx8mq_pins.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +#include <asm/mach-imx/gpio.h>
>>> +#include <asm/mach-imx/mxc_i2c.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <spl.h>
>>> +#include <power/pmic.h>
>>> +#include <power/pfuze100_pmic.h>
>>> +#include "../common/pfuze.h"
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
>>> +
>>> +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
>>> +
>>> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
>>> +
>>> +static iomux_v3_cfg_t const wdog_pads[] = {
>>> + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
>>> +};
>>> +
>>> +#ifdef CONFIG_FSL_QSPI
>>> +static iomux_v3_cfg_t const qspi_pads[] = {
>>> + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> +
>>> + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> +};
>>> +
>>> +int board_qspi_init(void)
>>> +{
>>> + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
>>> +
>>> + set_clk_qspi();
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +static iomux_v3_cfg_t const uart_pads[] = {
>>> + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +};
>>> +
>>> +int board_early_init_f(void)
>>> +{
>>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
>>> +
>>> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
>>> + set_wdog_reset(wdog);
>>> +
>>> + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int dram_init(void)
>>> +{
>>> + /* rom_pointer[1] contains the size of TEE occupies */
>>> + if (rom_pointer[1])
>>> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
>>> + else
>>> + gd->ram_size = PHYS_SDRAM_SIZE;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_FEC_MXC
>>> +#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
>>> +static iomux_v3_cfg_t const fec1_rst_pads[] = {
>>> + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> +};
>>> +
>>> +static void setup_iomux_fec(void)
>>> +{
>>> + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
>>> + ARRAY_SIZE(fec1_rst_pads));
>>> +
>>> + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
>>> + gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
>>> + udelay(500);
>>> + gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
>>> +}
>>> +
>>> +static int setup_fec(void)
>>> +{
>>> + struct iomuxc_gpr_base_regs *gpr =
>>> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>>> +
>>> + setup_iomux_fec();
>>> +
>>> + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
>>> + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
>>> + return set_clk_enet(ENET_125MHZ);
>>> +}
>>> +
>>> +int board_phy_config(struct phy_device *phydev)
>>> +{
>>> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
>>> +
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>>> +
>>> + if (phydev->drv->config)
>>> + phydev->drv->config(phydev);
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +int board_init(void)
>>> +{
>>> + board_qspi_init();
>>> +
>>> +#ifdef CONFIG_FEC_MXC
>>> + setup_fec();
>>> +#endif
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int board_mmc_get_env_dev(int devno)
>>> +{
>>> + return devno;
>>> +}
>>> +
>>> +int board_late_init(void)
>>> +{
>>> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>>> + env_set("board_name", "EVK");
>>> + env_set("board_rev", "iMX8MQ");
>>> +#endif
>>> +
>>> + return 0;
>>> +}
>>> diff --git a/board/freescale/mx8mq_evk/spl.c
>>> b/board/freescale/mx8mq_evk/spl.c
>>> new file mode 100644
>>> index 0000000000..522d076124
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/spl.c
>>> @@ -0,0 +1,233 @@
>>> +/*
>>> + * Copyright 2017 NXP
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <spl.h>
>>> +#include <asm/io.h>
>>> +#include <errno.h>
>>> +#include <asm/io.h>
>>> +#include <asm/mach-imx/iomux-v3.h>
>>> +#include <asm/arch/mx8mq_pins.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +#include <power/pmic.h>
>>> +#include <power/pfuze100_pmic.h>
>>> +#include "../common/pfuze.h"
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/mach-imx/gpio.h>
>>> +#include <asm/mach-imx/mxc_i2c.h>
>>> +#include <fsl_esdhc.h>
>>> +#include <mmc.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +__weak void ddr_init(void)
>>> +{
>>> +};
>>> +
>>
>> This weak could be dropped, it was surely for test purpose :-)
>
> I understand patch 23/23 about the ddr script, it is hard to be accepted.
> So I add a weak function here to avoid build failure if other 22 patches
> could be accepted. It may take long time to convert the ddr script to
> structure based.
Ok, understand.
>
> So would you like to me to drop it and keep 23/23 in V3, or keep the weak
> ddr_init and drop 23/23 in V3?
Thing is that this patch is dead code without DDR setup. I am ready to
merge reviewed patch, even if they add MX8M and there is not yet any
board using - theoretically, this is also dead code and I could not. But
this simplifies the development and you can reduce the number of patches
to be posted next time. But merging a board that is known to be broken
due to a missing part, it is nonsense. Board will be merged when we have
a suitable way to set the DDR controller.
Regards,
Stefano
>
>>
>>> +void spl_dram_init(void)
>>> +{
>>> + /* ddr init */
>>> + ddr_init();
>>> +}
>>> +
>>> +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
>>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>>> +struct i2c_pads_info i2c_pad_info1 = {
>>> + .scl = {
>>> + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
>>> + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
>>> + .gp = IMX_GPIO_NR(5, 14),
>>> + },
>>> + .sda = {
>>> + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
>>> + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
>>> + .gp = IMX_GPIO_NR(5, 15),
>>> + },
>>> +};
>>> +
>>> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
>>> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
>>> +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
>>> +
>>> +int board_mmc_getcd(struct mmc *mmc)
>>> +{
>>> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
>>> + int ret = 0;
>>> +
>>> + switch (cfg->esdhc_base) {
>>> + case USDHC1_BASE_ADDR:
>>> + ret = 1;
>>> + break;
>>> + case USDHC2_BASE_ADDR:
>>> + ret = !gpio_get_value(USDHC2_CD_GPIO);
>>> + return ret;
>>> + }
>>> +
>>> + return 1;
>>> +}
>>> +
>>> +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
>>> + PAD_CTL_FSEL2)
>>> +
>>> +static iomux_v3_cfg_t const usdhc1_pads[] = {
>>> + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> +};
>>> +
>>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>>> + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> +};
>>> +
>>> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
>>> + {USDHC1_BASE_ADDR, 0, 8},
>>> + {USDHC2_BASE_ADDR, 0, 4},
>>> +};
>>> +
>>> +int board_mmc_init(bd_t *bis)
>>> +{
>>> + int i, ret;
>>> + /*
>>> + * According to the board_mmc_init() the following map is done:
>>> + * (U-Boot device node) (Physical Port)
>>> + * mmc0 USDHC1
>>> + * mmc1 USDHC2
>>> + */
>>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>>> + switch (i) {
>>> + case 0:
>>> + init_clk_usdhc(0);
>>> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
>>> + imx_iomux_v3_setup_multiple_pads(
>>> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
>>> + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
>>> + gpio_direction_output(USDHC1_PWR_GPIO, 0);
>>> + udelay(500);
>>> + gpio_direction_output(USDHC1_PWR_GPIO, 1);
>>> + break;
>>> + case 1:
>>> + init_clk_usdhc(1);
>>> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
>>> + imx_iomux_v3_setup_multiple_pads(
>>> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
>>> + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
>>> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
>>> + udelay(500);
>>> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
>>> + break;
>>> + default:
>>> + printf("Warning: you configured more USDHC
>>> controllers(%d) than supported by the board\n", i + 1);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_POWER
>>> +#define I2C_PMIC 0
>>> +int power_init_board(void)
>>> +{
>>> + struct pmic *p;
>>> + int ret;
>>> + unsigned int reg;
>>> +
>>> + ret = power_pfuze100_init(I2C_PMIC);
>>> + if (ret)
>>> + return -ENODEV;
>>> +
>>> + p = pmic_get("PFUZE100");
>>> + ret = pmic_probe(p);
>>> + if (ret)
>>> + return -ENODEV;
>>> +
>>> + pmic_reg_read(p, PFUZE100_DEVICEID, ®);
>>> + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
>>> +
>>> + pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
>>> + if ((reg & 0x3f) != 0x18) {
>>> + reg &= ~0x3f;
>>> + reg |= 0x18;
>>> + pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
>>> + }
>>> +
>>> + ret = pfuze_mode_init(p, APS_PFM);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +void spl_board_init(void)
>>> +{
>>> + enable_tzc380();
>>
>> Just for my understanding: is this board specific ? Enabling the
>> TrustZone controller looks to me more general, but I am maybe wrong. Can
>> you better explain me this ? Thanks !
>
> If want to use TZC380 on i.MX, TZC380 needs to be enabled
> before DDR initialization. So I put it in spl_board_init.
>
> TZC380 enablement is not a must for all boards.
>
> We will enable TEE on i.MX8MQ EVK board, so need to enable TZC380.
>
> Thanks,
> Peng
>
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