From 0d0ea4a15605080f0418d601e6539d6555266475 Mon Sep 17 00:00:00 2001
From: Stefan Berzl <stefanbe...@gmail.com>
Date: Mon, 11 Dec 2017 23:41:04 +0100
Subject: [PATCH] stm32f4: Support over-drive mode in standard code path
The datasheet for the stm32f429-discovery says that the clock rate of
180 Mhz is only attainable when the system is switched to over-drive,
so I added support for that.
Signed-off-by: Stefan Berzl <stefanbe...@gmail.com>
---
arch/arm/include/asm/arch-stm32f4/stm32.h | 5 ---
arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 4 +-
arch/arm/mach-stm32/stm32f4/clock.c | 55 +++++++++++++++++++--------
3 files changed, 41 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h
b/arch/arm/include/asm/arch-stm32f4/stm32.h
index e9f3aabb6f..f5bdaeb895 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -42,11 +42,6 @@ struct stm32_u_id_regs {
u32 u_id_high;
};
-struct stm32_pwr_regs {
- u32 cr;
- u32 csr;
-};
-
/*
* Registers access macros
*/
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
index bfe54698b3..9fa5a5b06a 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
@@ -16,8 +16,8 @@
#define PWR_CSR1_ODSWRDY BIT(17)
struct stm32_pwr_regs {
- u32 cr1; /* power control register 1 */
- u32 csr1; /* power control/status register 2 */
+ u32 cr; /* power control register */
+ u32 csr; /* power control/status register */
};
#endif /* __STM32_PWR_H_ */
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c
b/arch/arm/mach-stm32/stm32f4/clock.c
index 774591d6a5..706d716fd2 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
+#include <asm/arch/stm32_pwr.h>
#define RCC_CR_HSION (1 << 0)
#define RCC_CR_HSEON (1 << 16)
@@ -88,25 +89,31 @@
#if (CONFIG_STM32_HSE_HZ == 8000000)
#if (CONFIG_SYS_CLK_FREQ == 180000000)
/* 180 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 360,
- .pll_p = 2,
- .pll_q = 8,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
+struct stm32_clk_info stm32f4_clk_info = {
+ .sys_pll_psc = {
+ .pll_m = 8,
+ .pll_n = 360,
+ .pll_p = 2,
+ .pll_q = 8,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2,
+ },
+ .has_overdrive = true
};
#else
/* default 168 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 336,
- .pll_p = 2,
- .pll_q = 7,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
+struct stm32_clk_info stm32f4_clk_info = {
+ .sys_pll_psc = {
+ .pll_m = 8,
+ .pll_n = 336,
+ .pll_p = 2,
+ .pll_q = 7,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2
+ },
+ .has_overdrive = false
};
#endif
#else
@@ -116,6 +123,8 @@ struct pll_psc sys_pll_psc = {
int configure_clocks(void)
{
+ struct pll_psc sys_pll_psc = stm32f4_clk_info.sys_pll_psc;
+
/* Reset RCC configuration */
setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
@@ -151,6 +160,20 @@ int configure_clocks(void)
while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
;
+ if (stm32f4_clk_info.has_overdrive) {
+ /* Enable Over-drive mode */
+ setbits_le32(&STM32_PWR->cr, PWR_CR1_ODEN);
+
+ while (!(readl(&STM32_PWR->csr) & PWR_CSR1_ODRDY))
+ ;
+
+ /* Enable the Over-drive switch */
+ setbits_le32(&STM32_PWR->cr, PWR_CR1_ODSWEN);
+
+ while (!(readl(&STM32_PWR->csr) & PWR_CSR1_ODSWRDY))
+ ;
+ }
+
stm32_flash_latency_cfg(5);
clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
--
2.15.1
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