> -----Original Message----- > From: Fabio Estevam [mailto:feste...@gmail.com] > Sent: Tuesday, January 02, 2018 8:52 AM > To: sba...@denx.de > Cc: u-boot@lists.denx.de; ste...@agner.ch; Peng Fan <peng....@nxp.com>; > Fabio Estevam <fabio.este...@nxp.com> > Subject: [PATCH] mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL > > From: Fabio Estevam <fabio.este...@nxp.com> > > i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access > it. > > Signed-off-by: Fabio Estevam <fabio.este...@nxp.com> > --- > arch/arm/mach-imx/mx6/ddr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c > index 52a9a25..39dbd2f 100644 > --- a/arch/arm/mach-imx/mx6/ddr.c > +++ b/arch/arm/mach-imx/mx6/ddr.c > @@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width, #define > MR(val, ba, cmd, cs1) \ > ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) > #define MMDC1(entry, value) do { \ > - if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \ > + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \ > mmdc1->entry = value; \ > } while (0) > > @@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo > *sysinfo, > u16 mem_speed = ddr3_cfg->mem_speed; > > mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; > - if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) > + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) > mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
Reviewed-by: Peng Fan <peng....@nxp.com> > > /* Limit mem_speed for MX6D/MX6Q */ > -- > 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
