These nodes were previously in an unused file specific to the Pine64.
Move them to the base SoC device tree for use by other boards. Require
individual boards to enable the emac and provide a pin configuration.
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 50 -------------------------
arch/arm/dts/sun50i-a64.dtsi | 28 ++++++++++++++
2 files changed, 28 insertions(+), 50 deletions(-)
delete mode 100644 arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
deleted file mode 100644
index 9c61beac01..0000000000
--- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
+++ /dev/null
@@ -1,50 +0,0 @@
-/ {
- aliases {
- ethernet0 = &emac;
- };
-
- soc {
- emac: ethernet@01c30000 {
- compatible = "allwinner,sun50i-a64-emac";
- reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
- reg-names = "emac", "syscon";
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_BUS_EMAC>;
- reset-names = "ahb";
- clocks = <&ccu CLK_BUS_EMAC>;
- clock-names = "ahb";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
- phy = <&phy1>;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
- };
-};
-
-&pio {
- rmii_pins: rmii_pins {
- allwinner,pins = "PD10", "PD11", "PD13", "PD14",
- "PD17", "PD18", "PD19", "PD20",
- "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <3>;
- allwinner,pull = <0>;
- };
-
- rgmii_pins: rgmii_pins {
- allwinner,pins = "PD8", "PD9", "PD10", "PD11",
- "PD12", "PD13", "PD15",
- "PD16", "PD17", "PD18", "PD19",
- "PD20", "PD21", "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <3>;
- allwinner,pull = <0>;
- };
-};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 02061cc608..c686707cf5 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -51,6 +51,10 @@
#address-cells = <1>;
#size-cells = <1>;
+ aliases {
+ ethernet0 = &emac;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -267,6 +271,16 @@
interrupt-controller;
#interrupt-cells = <3>;
+ emac_rgmii_pins: emac_rgmii_pins {
+ allwinner,pins = "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD15",
+ "PD16", "PD17", "PD18", "PD19",
+ "PD20", "PD21", "PD22", "PD23";
+ allwinner,function = "emac";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
i2c1_pins: i2c1_pins {
pins = "PH2", "PH3";
function = "i2c1";
@@ -401,6 +415,20 @@
#size-cells = <0>;
};
+ emac: ethernet@01c30000 {
+ compatible = "allwinner,sun50i-a64-emac";
+ reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
+ reg-names = "emac", "syscon";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "ahb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
--
2.13.6
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