Dear Wolfgang Wegner,

In message <20100119131716.gc23...@leila.ping.de> you wrote:
> 
> The problem turned out to be a simple SDRAM setup problem.
> I had set "burst read to read/precharge delay" and "burst write
> to read/write/precharge delay" by 1 too low.
> 
> Don't know how I messed these values up, but these lead to all
> memory accesses in single-step mode and via BDM to work correctly
> but gave erroneous results in real program execution.
> 
> [note to self: in case of strange errors, always check memory
> interface. If triple-checked: check again...]

Congrats for fixing it - note that y ou are not the first one to
discover this. There is a reason why this topic has a top entry in the
FAQ.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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