Hi Simon, > On 09.02.2018 23:14, Lukasz Majewski wrote: > > All Socfpga boards from ./include/configs/socfpga_* define > > CONFIG_HW_WATCHDOG. > > To ease CONFIG_HW_WATCHDOG conversion to Kconfig select it in > > config ARCH_SOCFPGA (arch/arm/Kconfig) section. > > I do have board configs where the internal watchdog is not used and > should be disabled (because there's an external one). Also, given > that this is an FPGA, I suppose having non-upstreamed boards is not > uncommon.
I must admit that this patch I did after looking on the socfpga pattern in the current upstream. It seems like all boards there use HW_WATCHDOG. > > I'm not too familiar with these settings though: can I leave the > watchdog disabled when CONFIG_HW_WATCHDOG is off? Before, I just > haven't enabled this in my own board config... I think that I will prepare next revision of this patch with just simple ./tools/moveconfig.py output (without blindly selecting HW_WATCHDOG on all socfpga devices). In that way we will preserve the current behaviour. Best regards, Łukasz Majewski > > Simon > > > > > Signed-off-by: Lukasz Majewski <lu...@denx.de> > > --- > > > > Changes in v2: > > - None > > > > arch/arm/Kconfig | 1 + > > include/configs/socfpga_arria10_socdk.h | 2 -- > > include/configs/socfpga_arria5_socdk.h | 2 -- > > include/configs/socfpga_cyclone5_socdk.h | 2 -- > > include/configs/socfpga_de0_nano_soc.h | 2 -- > > include/configs/socfpga_de10_nano.h | 2 -- > > include/configs/socfpga_de1_soc.h | 2 -- > > include/configs/socfpga_is1.h | 2 -- > > include/configs/socfpga_mcvevk.h | 2 -- > > include/configs/socfpga_sockit.h | 2 -- > > include/configs/socfpga_socrates.h | 2 -- > > include/configs/socfpga_sr1500.h | 2 -- > > include/configs/socfpga_vining_fpga.h | 2 -- > > 13 files changed, 1 insertion(+), 24 deletions(-) > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 225f57e847..b4c79d6499 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -702,6 +702,7 @@ config ARCH_SOCFPGA > > select DM_SPI_FLASH > > select DM_SPI > > select ENABLE_ARM_SOC_BOOT0_HOOK > > + select HW_WATCHDOG > > select ARCH_EARLY_INIT_R > > select ARCH_MISC_INIT > > select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION > > diff --git a/include/configs/socfpga_arria10_socdk.h > > b/include/configs/socfpga_arria10_socdk.h index > > 83718dd2c9..82bb48b277 100644 --- > > a/include/configs/socfpga_arria10_socdk.h +++ > > b/include/configs/socfpga_arria10_socdk.h @@ -9,8 +9,6 @@ > > > > #include <asm/arch/base_addr_a10.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Booting Linux */ > > #define CONFIG_LOADADDR 0x01000000 > > #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > > diff --git a/include/configs/socfpga_arria5_socdk.h > > b/include/configs/socfpga_arria5_socdk.h index > > 6b6d54b97b..cd5aac65e9 100644 --- > > a/include/configs/socfpga_arria5_socdk.h +++ > > b/include/configs/socfpga_arria5_socdk.h @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB on SoCDK */ > > diff --git a/include/configs/socfpga_cyclone5_socdk.h > > b/include/configs/socfpga_cyclone5_socdk.h index > > 018a0c3bb4..9c5bd648e3 100644 --- > > a/include/configs/socfpga_cyclone5_socdk.h +++ > > b/include/configs/socfpga_cyclone5_socdk.h @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB on SoCDK */ > > diff --git a/include/configs/socfpga_de0_nano_soc.h > > b/include/configs/socfpga_de0_nano_soc.h index > > 275ed7ffeb..e5db00e366 100644 --- > > a/include/configs/socfpga_de0_nano_soc.h +++ > > b/include/configs/socfpga_de0_nano_soc.h @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB */ > > diff --git a/include/configs/socfpga_de10_nano.h > > b/include/configs/socfpga_de10_nano.h index bb50fcf1ff..656af1104d > > 100644 --- a/include/configs/socfpga_de10_nano.h > > +++ b/include/configs/socfpga_de10_nano.h > > @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB */ > > diff --git a/include/configs/socfpga_de1_soc.h > > b/include/configs/socfpga_de1_soc.h index 05975c9bde..f57b950425 > > 100644 --- a/include/configs/socfpga_de1_soc.h > > +++ b/include/configs/socfpga_de1_soc.h > > @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB */ > > diff --git a/include/configs/socfpga_is1.h > > b/include/configs/socfpga_is1.h index 46f5f135dd..dc318e50dc 100644 > > --- a/include/configs/socfpga_is1.h > > +++ b/include/configs/socfpga_is1.h > > @@ -9,8 +9,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x10000000 > > > > diff --git a/include/configs/socfpga_mcvevk.h > > b/include/configs/socfpga_mcvevk.h index 404f064e94..f13463b8b0 > > 100644 --- a/include/configs/socfpga_mcvevk.h > > +++ b/include/configs/socfpga_mcvevk.h > > @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB on MCV */ > > diff --git a/include/configs/socfpga_sockit.h > > b/include/configs/socfpga_sockit.h index b4f31c42c5..0bbc7e0105 > > 100644 --- a/include/configs/socfpga_sockit.h > > +++ b/include/configs/socfpga_sockit.h > > @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB on SoCDK */ > > diff --git a/include/configs/socfpga_socrates.h > > b/include/configs/socfpga_socrates.h index ebb9ac588d..b66108d0cc > > 100644 --- a/include/configs/socfpga_socrates.h > > +++ b/include/configs/socfpga_socrates.h > > @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB on SoCrates */ > > diff --git a/include/configs/socfpga_sr1500.h > > b/include/configs/socfpga_sr1500.h index 39bf612291..871f587d45 > > 100644 --- a/include/configs/socfpga_sr1500.h > > +++ b/include/configs/socfpga_sr1500.h > > @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB on SR1500 */ > > diff --git a/include/configs/socfpga_vining_fpga.h > > b/include/configs/socfpga_vining_fpga.h index > > 0c76a77525..1197b40b58 100644 --- > > a/include/configs/socfpga_vining_fpga.h +++ > > b/include/configs/socfpga_vining_fpga.h @@ -8,8 +8,6 @@ > > > > #include <asm/arch/base_addr_ac5.h> > > > > -#define CONFIG_HW_WATCHDOG > > - > > /* Memory configurations */ > > #define PHYS_SDRAM_1_SIZE 0x40000000 /* > > 1GiB on VINING_FPGA */ > Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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