On Thu, Feb 08, 2018 at 05:20:47PM +0100, patrice.chot...@st.com wrote: > From: Patrice Chotard <patrice.chot...@st.com> > > Initially, 48Mhz for SDIO clock was generated from SAI pll for > STM32F469 and STM32F746 SoCs, but this solution was not suitable > for STM32F429 SoCs. > > A generic solution is to used the PLL_Q output as 48Mhz clock > for all STM32F SOCs family. > > Signed-off-by: Patrice Chotard <patrice.chot...@st.com>
Applied to u-boot/master, thanks! -- Tom
signature.asc
Description: PGP signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
