On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Jaehoon Chung <jh80.ch...@samsung.com>
Cc: Masahiro Yamada <yamada.masah...@socionext.com>
---
drivers/mmc/matsushita-common.c | 3 ++-
drivers/mmc/matsushita-common.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/matsushita-common.c b/drivers/mmc/matsushita-common.c
index 449f533d1b..7e05b1f3d1 100644
--- a/drivers/mmc/matsushita-common.c
+++ b/drivers/mmc/matsushita-common.c
@@ -542,7 +542,8 @@ static void matsu_sd_set_clk_rate(struct matsu_sd_priv
*priv,
divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
if (divisor <= 1)
- val = MATSU_SD_CLKCTL_DIV1;
+ val = (priv->caps & MATSU_SD_CAP_RCAR) ?
+ MATSU_SD_CLKCTL_RCAR_DIV1 : MATSU_SD_CLKCTL_DIV1;
else if (divisor <= 2)
val = MATSU_SD_CLKCTL_DIV2;
else if (divisor <= 4)
diff --git a/drivers/mmc/matsushita-common.h b/drivers/mmc/matsushita-common.h
index c23dc1a79a..a10ad202c8 100644
--- a/drivers/mmc/matsushita-common.h
+++ b/drivers/mmc/matsushita-common.h
@@ -63,6 +63,7 @@
#define MATSU_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
#define MATSU_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
#define MATSU_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
+#define MATSU_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
#define MATSU_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when
unused */
#define MATSU_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
#define MATSU_SD_SIZE 0x04c /* block size */
--
2.16.2
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