On 04/19/2018 11:50 AM, Ley Foon Tan wrote: > Add SPL driver support for Stratix SoC > > Signed-off-by: Chin Liang See <chin.liang....@intel.com> > Signed-off-by: Ley Foon Tan <ley.foon....@intel.com> > --- > arch/arm/mach-socfpga/Makefile | 4 + > arch/arm/mach-socfpga/include/mach/firewall_s10.h | 84 +++++++++ > arch/arm/mach-socfpga/spl_s10.c | 205 > +++++++++++++++++++++ > 3 files changed, 293 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h > create mode 100644 arch/arm/mach-socfpga/spl_s10.c > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > index b669d43..35b124a 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile > @@ -40,6 +40,7 @@ obj-y += system_manager_s10.o > obj-y += wrap_pinmux_config_s10.o > obj-y += wrap_pll_config_s10.o > endif > + > ifdef CONFIG_SPL_BUILD > ifdef CONFIG_TARGET_SOCFPGA_GEN5 > obj-y += spl_gen5.o > @@ -51,6 +52,9 @@ endif > ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 > obj-y += spl_a10.o > endif > +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 > +obj-y += spl_s10.o > +endif > endif > > ifdef CONFIG_TARGET_SOCFPGA_GEN5 > diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h > b/arch/arm/mach-socfpga/include/mach/firewall_s10.h > new file mode 100644 > index 0000000..70aa9a6 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h > @@ -0,0 +1,84 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * > + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> > + * > + */ > + > +#ifndef _FIREWALL_S10_ > +#define _FIREWALL_S10_ > + > +struct socfpga_firwall_l4_per { > + u32 nand; /* 0x00 */ > + u32 nand_data; > + u32 _pad_0x8; > + u32 usb0; > + u32 usb1; /* 0x10 */ > + u32 _pad_0x14; > + u32 _pad_0x18; > + u32 spim0; > + u32 spim1; /* 0x20 */ > + u32 spis0; > + u32 spis1; > + u32 emac0; > + u32 emac1; /* 0x30 */ > + u32 emac2; > + u32 _pad_0x38; > + u32 _pad_0x3c; > + u32 sdmmc; /* 0x40 */ > + u32 gpio0; > + u32 gpio1; > + u32 _pad_0x4c; > + u32 i2c0; /* 0x50 */ > + u32 i2c1; > + u32 i2c2; > + u32 i2c3; > + u32 i2c4; /* 0x60 */ > + u32 timer0; > + u32 timer1; > + u32 uart0; > + u32 uart1; /* 0x70 */ > +}; > + > +struct socfpga_firwall_l4_sys { > + u32 _pad_0x00; /* 0x00 */ > + u32 _pad_0x04; > + u32 dma_ecc; > + u32 emac0rx_ecc; > + u32 emac0tx_ecc; /* 0x10 */ > + u32 emac1rx_ecc; > + u32 emac1tx_ecc; > + u32 emac2rx_ecc; > + u32 emac2tx_ecc; /* 0x20 */ > + u32 _pad_0x24; > + u32 _pad_0x28; > + u32 nand_ecc; > + u32 nand_read_ecc; /* 0x30 */ > + u32 nand_write_ecc; > + u32 ocram_ecc; > + u32 _pad_0x3c; > + u32 sdmmc_ecc; /* 0x40 */ > + u32 usb0_ecc; > + u32 usb1_ecc; > + u32 clock_manager; > + u32 _pad_0x50; /* 0x50 */ > + u32 io_manager; > + u32 reset_manager; > + u32 system_manager; > + u32 osc0_timer; /* 0x60 */ > + u32 osc1_timer; > + u32 watchdog0; > + u32 watchdog1; > + u32 watchdog2; /* 0x70 */ > + u32 watchdog3; > +}; > + > +#define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) > +#define FIREWALL_BRIDGE_DISABLE_ALL (~0) > + > +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7004688 > +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7018628 > + > +#define CCU_ADMASK_P_MASK (BIT(0)) > +#define CCU_ADMASK_NS_MASK (BIT(1))
Drop outer parenthesis > + > +#endif /* _FIREWALL_S10_ */ > diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c > new file mode 100644 > index 0000000..3b3833d > --- /dev/null > +++ b/arch/arm/mach-socfpga/spl_s10.c > @@ -0,0 +1,205 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> > + * > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/u-boot.h> > +#include <asm/utils.h> > +#include <image.h> > +#include <asm/arch/reset_manager.h> > +#include <spl.h> > +#include <asm/arch/system_manager.h> > +#include <asm/arch/clock_manager.h> > +#include <asm/arch/sdram_s10.h> > +#include <asm/arch/mailbox_s10.h> > +#include <asm/arch/firewall_s10.h> > +#include <watchdog.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static const struct socfpga_firwall_l4_per *firwall_l4_per_base = > + (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; > +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = > + (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; > +static struct socfpga_system_manager *sysmgr_regs = > + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > + > +u32 spl_boot_device(void) > +{ > + /* TODO: Get from SDM or handoff */ > + return BOOT_DEVICE_MMC1; > +} > + > +#ifdef CONFIG_SPL_MMC_SUPPORT > +u32 spl_boot_mode(const u32 boot_device) > +{ > +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) > + return MMCSD_MODE_FS; > +#else > + return MMCSD_MODE_RAW; > +#endif > +} > +#endif > + > +void board_init_f(ulong dummy) > +{ > + const struct cm_config *cm_default_cfg = cm_get_default_config(); > + > +#ifdef CONFIG_HW_WATCHDOG > + /* Ensure watchdog is paused when debugging is happening */ > + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); > + > + /* Enable watchdog before initializing the HW */ > + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); > + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); > + hw_watchdog_init(); > +#endif > + > + /* ensure all processors are not released prior Linux boot */ > + writeq(0, CPU_RELEASE_ADDR); > + > + socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); > + timer_init(); > + > + populate_sysmgr_pinmux(); > + > + /* configuring the HPS clocks */ > + cm_basic_init(cm_default_cfg); > + > + /* enable console uart printing */ > +#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS) Yoda notation, please fix. Also, shouldn't the reset controller handle this ? > + socfpga_per_reset(SOCFPGA_RESET(UART0), 0); > + /* enables nonsecure access to UART0 */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0); > +#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS) > + socfpga_per_reset(SOCFPGA_RESET(UART1), 0); > + /* enables nonsecure access to UART1 */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1); > +#endif > + > + preloader_console_init(); > + cm_print_clock_quick_summary(); This function doesn't fit on my pivoted 4k screen with small font, it is clearly too long. Please split it. > + /* enable non-secure interface to DMA330 DMA and peripherals */ > + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); > + writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); > + /* enable DMA330 DMA */ > + socfpga_per_reset(SOCFPGA_RESET(DMA), 0); > + > + /* > + * The following lines of code will enable non-secure access > + * to nand, usb, spi, emac, sdmmc, gpio, i2c, and timers. This > + * is needed as most OS run in non-secure mode. Thus we need to > + * enable non-secure access to these peripherals in order for the > + * OS to use these peripherals. > + */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->nand_data); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb0); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->usb1); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim0); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->spim1); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio0); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->gpio1); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c2); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c3); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c4); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer0); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->timer1); Turn this into a table ? > + /* enables nonsecure access to clock mgr */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager); > + > + /* enables nonsecure access to reset mgr */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->reset_manager); > + > + /* enables nonsecure access to system mgr */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->system_manager); > + > + /* enables nonsecure access to OCRAM */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc); > + > + /* enables nonsecure access to all the emacs */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc); > + > + /* enables nonsecure access to SMMU */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->io_manager); > + > + /* enables nonsecure access to watchdog */ > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog0); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog1); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog2); > + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->watchdog3); > + > + /* enables SDMMC */ > + socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0); > + socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); > + /* enable usb0 and usb1 */ > + socfpga_per_reset(SOCFPGA_RESET(USB0), 0); > + socfpga_per_reset(SOCFPGA_RESET(USB1), 0); > + socfpga_per_reset(SOCFPGA_RESET(USB0_OCP), 0); > + socfpga_per_reset(SOCFPGA_RESET(USB1_OCP), 0); > + /* enable SPIM1 */ > + socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); See below. > + /* disable lwsocf2fpga and soc2fpga bridge security */ > + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); > + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); > + > + /* disable SMMU security */ > + writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); > + > + /* disable ocram security at CCU for non secure access */ > + clrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR, > + CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); > + clrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR, > + CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); > + > + /* enable i2c1 */ > + socfpga_per_reset(SOCFPGA_RESET(I2C1), 0); > + > + /* Take GPIO0 & GPIO1 out of reset */ > + socfpga_per_reset(SOCFPGA_RESET(GPIO0), 0); > + socfpga_per_reset(SOCFPGA_RESET(GPIO1), 0); Shouldn't this be done by the reset framework ? > + /* enable SPIM0 and SPIM1 */ > + socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); > + socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); You ungated this SPI block already like 20 lines above. > + puts("DDR: Initializing Hard Memory Controller\n"); > + if (sdram_mmr_init_full(0)) { > + puts("DDR: Initialization failed.\n"); > + hang(); > + } > + > + gd->ram_size = sdram_calculate_size(); > + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); > + > + /* Sanity check ensure correct SDRAM size specified */ > + puts("DDR: Running SDRAM size sanity check\n"); > + if (get_ram_size(0, gd->ram_size) != gd->ram_size) { > + puts("DDR: SDRAM size check failed!\n"); > + hang(); > + } > + puts("DDR: SDRAM size check passed!\n"); You can probably turn most of those ad-hoc prints into debug()s. > + > +#ifdef CONFIG_CADENCE_QSPI > + mbox_init(); > + mbox_qspi_open(); > +#endif > +} > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot